coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-08-07	intel/nehalem,sandybridge: Move stage_cache support function	Kyösti Mälkki
2019-06-21	cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35	Elyes HAOUAS
2019-05-27	cpu/intel/model_2065x: Put stage cache in TSEG	Arthur Heymans
2019-05-27	cpu/intel/model_2065x: Use parallel MP init	Arthur Heymans
2019-01-22	cpu/intel/model_206ax: Use parallel MP init	Arthur Heymans
2018-10-11	src: Move common IA-32 MSRs to <cpu/x86/msr.h>	Elyes HAOUAS
2018-05-01	Fix freeze during chipset lockdown on Nehalem	Matthias Gazzari
2018-04-11	Revert "model_206ax: Use parallel MP init"	Arthur Heymans
2018-04-11	model_206ax: Use parallel MP init	Arthur Heymans
2017-03-16	cpu/intel: Indent with tabs	Lee Leahy
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-28	Migrate 2065x to SMM_MODULES	Vladimir Serbinenko
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-03-13	cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY	Alexander Couzens
2015-02-18	cpu/intel/model_2065x\|nehalem: remove unsupported MSR_PP0/MSR_PP1	Alexander Couzens
2013-11-23	Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.	Vladimir Serbinenko
2013-06-13	Add support for Intel Nehalem CPU	Vladimir Serbinenko