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2021-06-16cpu/intel/haswell: Select `HAVE_DISPLAY_MTRRS`Angel Pons
This option is valid for Broadwell as well as Haswell. Change-Id: I4f1e9663806bae279f6aca36f09a0c989c12e507 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16cpu/intel/haswell: Enable MCA loggingAngel Pons
Intel document 493770 (Haswell BIOS Writer's Guide) revision 1.8.0 recommends writing all ones to the IA32_MCi_CTL registers in order to enable all MCA error reporting. Change-Id: Ib5d2c759483026b5b4804c5a4b2b969d2269af22 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55463 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-07cpu/intel/haswell/acpi.c: Do not report P_BLKAngel Pons
Even if IO MWAIT redirection were enabled, the base address is wrong. Moreover, the register resource descriptors for all reported C-states use the FFixedHW address space, not I/O. Change-Id: Ic2faaafbe4928994aeeab8098d8e0fb6703d203d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-26Add Kconfig TPMKyösti Mälkki
Defined as TPM1 || TPM2. Change-Id: I18c26d6991c2ccf782a515a8e90a3eb82b53b0e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-10cpu/intel/haswell: Use new fixed BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5fb31f88bbf7c2f1e44924ca2d3169257a9598dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-14cpu/intel/haswell: Constify ACPI c-state arraysAngel Pons
Change-Id: I5538d8279392238e59aba99ade4b5fe13f250ca8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49805 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14cpu/intel/haswell: Drop c-state table indirectionAngel Pons
Accessing it directly allows proper bounds-checking. Change-Id: Ifb539051e4a91ddcdb5ffec4850dc2fb30482aea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49804 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12cpu/intel/haswell/acpi.c: Correct `get_cores_per_package`Angel Pons
CPUID result does not change when HyperThreading is disabled on HT-enabled CPUs, which breaks `generate_cpu_entries`. Use MSR 0x35 instead, which returns the currently-enabled core and thread count. Also rename the function to `get_logical_cores_per_package, which is more accurate. Based on commit 920d2b77f2 (cpu/intel/206ax/acpi.c: Fix get_cores_per_package). The MSR definition is the same for Sandy Bridge and Haswell. Change-Id: I5e1789d3037780b4285c9e367ff0e2b0d4365b39 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49099 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11src: Remove unused <arch/cpu.h>Elyes HAOUAS
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-24soc/intel/broadwell: Move romstage.c to HaswellAngel Pons
Broadwell no longer has CPU code. Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46951 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/broadwell: Use Haswell CPU headersAngel Pons
Now that the boards use Haswell's CPU code, Broadwell can be updated. Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46949 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24cpu/intel/haswell: Add Broadwell CPUIDs and microcodeAngel Pons
Broadwell can now use the Haswell CPU driver. Change-Id: I36138cab72b1e3ad0ff7f6434996f5ce00de9d0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46942 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24cpu/intel/haswell: Set C9/C10 vccminAngel Pons
Backport commit ab7586fa26 (broadwell: Set C9/C10 vccmin) to Haswell. Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46922 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24cpu/intel/haswell: Add fast ramp voltage for BroadwellAngel Pons
Backport commit 55228ba4b4 (broadwell: Changes from 2.2.0 ref code) to Haswell, to eventually migrate Broadwell to use the same Haswell code. Change-Id: I03d9ff16bcaab9091bd723ce933aa3f2d71e29b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46921 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22cpu/intel/haswell: Enable timed MWAIT if supportedAngel Pons
Broadwell code unconditionally enables timed MWAIT, but not all Haswell steppings support it. In preparation for merging Haswell and Broadwell, also enable timed MWAIT on Haswell code, but only if it is supported. Change-Id: I1d11d62f1801d65ae4d5623994fd55fd35e8f34a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46916 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21cpu/intel/haswell: Clean up CPUID definitionsAngel Pons
The `mobile` suffix is misleading, since desktop CPUs share the same CPUIDs. Remove unused stepping IDs and add the full CPUIDs instead. Finally, add Broadwell CPUIDs in preparation for merging CPU code. Note that steppings for Haswell in various comments are incorrect. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46915 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21cpu/intel/haswell: Add s0ix supportAngel Pons
Backport Broadwell's s0ix support to Haswell in preparation to unify both platforms' CPU code. Note that only ULT variants support s0ix. This option is currently unused, but will be put to use in subsequent commits, when switching Broadwell mainboards to use Haswell's CPU code. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46924 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15cpu/intel/haswell/acpi.c: Use C-state enum definitionsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I0ca98cbe45e10d233607f68923f08752fdda9698 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46923 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15cpu/intel/haswell: Factor out ACPI C-state valuesAngel Pons
There's no need to have them in the devicetree. ACPI generation can now be simplified even further, and is done in subsequent commits. Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11cpu/intel/haswell: Add delay for TPM before Flex Ratio rebootAngel Pons
Commit 542307b815 (broadwell: Add small delay before Flex Ratio reboot) introduced a workaround for Broadwell. Implement it on Haswell as well. Since this is only necessary when a TPM is present on a system, only do the delay (which is not that small, to be honest) on TPM-enabled builds. Change-Id: Id8b58e9fa2a1c81989305f5b4b765b82c01e1596 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46941 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11cpu/intel/haswell: Allow tuning VR for C-state operationsAngel Pons
Apply commit ff0f460e76 (broadwell: Add configuration for tuning VR for C-state operations) to Haswell, in preparation for unification. Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46920 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11cpu/intel/haswell: Raise PSI1 threshold to 20AAngel Pons
Haswell reference code version 1.9.0 uses the same value as Broadwell. Change-Id: I979ea1b4ba2962bd0c55cfb9d0c291f32cf5fcad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46919 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11cpu/intel/haswell: Enable turbo ratio if availableAngel Pons
Commit 7f28e4ee01 (broadwell: Enable turbo ratio if available) is also applicable to Haswell, since the MSR definitions are the same for both. Change-Id: Ic5f30a5b06301449253bbfb9ed58c6b35a767763 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46918 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSRAngel Pons
The MSR only needs to be set when IO MWAIT redirection is to be enabled. This was copied from Sandy Bridge, which already had this inconsistency. Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46917 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10cpu/intel/haswell/haswell.h: Align with BroadwellAngel Pons
Sort MSR definitions, move MCHBAR registers to northbridge and relocate C-state latency macros into the header. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46914 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10cpu/intel/haswell: Align cosmetics with BroadwellAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3eb522a48edf9e8fc7664141253ae4e2072d71fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46913 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10cpu/intel/haswell: Do not determine CPU type at runtimeAngel Pons
It is already known at compile-time. Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46912 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07cpu/intel/haswell: Rename `HASWELL_BCLK` to `CPU_BCLK`Angel Pons
This is just to ease merging with Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I9239489fe48f04714e6626b57ef07ca8b3013024 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46910 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06cpu/intel/x/chip.h: Drop unused `disable_acpi` settingAngel Pons
It is not used anywhere. Drop it. Change-Id: I92a72a46db237cf855491a664cdfadca34306f6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49087 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22cpu/intel/common: Fill cpu voltage in SMBIOS tablesPatrick Rudolph
Introduce a weak function to let the platform code provide the processor voltage in 100mV units. Implement the function on Intel platforms using the MSR_PERF_STATUS msr. On other platforms the processor voltage still reads as unknown. Tested on Intel CFL. The CPU voltage is correctly advertised. Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-03cpu/intel/haswell: Move smmrelocate.c MSR definitions to headerAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46733 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23haswell/broadwell: Fix typos of `BCLK`Angel Pons
Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-16include/cpu/x86: introduce new helper for (un)setting MSRsMichael Niewöhner
msr_set_bit can only set single bits in MSRs and causes mixing of bit positions and bitmasks in the MSR header files. Thus, replace the helper by versions which can unset and set whole MSR bitmasks, just like the "and-or"-helper, but in the way commit 64a6b6c was done (inversion done in the helper). This helps keeping the MSR macros unified in bitmask style. In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get added. The few uses of msr_set_bit have been replaced by the new version, while the used macros have been converted accordingly. Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14haswell/lynxpoint: Align cosmetics with BroadwellAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-27cpu/intel/haswell/smmrelocate.c: Spell `CPU` in uppercaseAngel Pons
This is to align Haswell and Broadwell. Change-Id: I8585597a8de164fb8d3b33db0d95c3aaf3cd7afc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45711 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27cpu/intel/haswell/haswell_init.c: Align printk's with BroadwellAngel Pons
Change-Id: I09f4fc5af28b20663b87d18852d585121feaab09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21src/cpu: Drop unneeded empty linesElyes HAOUAS
Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-08-30cpu/intel/haswell: Set LT_LOCK_MEMORY MSR on finalize stepAngel Pons
This is a security lock and is required for TXT, among other things. Tested on Asrock B85M Pro4, still boots. Change-Id: I7b2e8a60ce92cbf523c520be0b365f28413b9624 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44884 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21cpu/intel/haswell: Select HAVE_ASAN_IN_ROMSTAGEHarshit Sharma
Enable ASan in romstage for haswell as it has been tested on Lenovo ThinkPad T440P. Change-Id: I6eae242c71f41c9159658ae68d61b4036ad42d42 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-03cpu/intel/haswell: add Crystal Well CPU IDsIru Cai
Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26cpu,soc/intel: Drop select SMPKyösti Mälkki
Implicitly selected with MAX_CPUS != 1. Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-10cpu/intel/haswell/finalize.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I3fc616eeb975aae7a5937f8b555ae554010d8dd3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-08haswell: relocate `romstage_common` to northbridgeAngel Pons
Other platforms do this as well. It will ease refactoring on follow-ups. Change-Id: I643982a58c6f5370c78acef93740f27df001a06d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08nb/intel/haswell: Drop unnecessary variableAngel Pons
The "normalized" boot mode is only used in a single place, so there's no need to use a variable. Also, reword the associated comment, which seems to be unnecessarily vague: the hardcoded assumptions are inside the MRC. Change-Id: I260d10f231f5de765d2675416d7047717d391d8f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08haswell: drop unused function parameterAngel Pons
The `chipset_type` parameter is ignored. Change-Id: Ia3d217178cc9caabf232b3a59f505229cc03135f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-06-16sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-15haswell boards: Factor out MAX_CPUSAngel Pons
ULT only has 4 threads, but we are not changing it here to preserve binary reproducibility. Change-Id: I041c5dff2de514244f9c919c4c475cca979c34ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41842 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15arch/x86: Remove NO_FIXED_XIP_ROM_SIZEKyösti Mälkki
The variable SETUP_XIP_CACHE provides us a working alternative. Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-06src: Remove unused 'include <cpu/x86/mtrr.h>'Elyes HAOUAS
Change-Id: I3f08b9cc34582165785063580b3356135030f63e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian
2020-06-06cpu/intel/haswell: Remove unused 'include <cpu/x86/bist.h>'Elyes HAOUAS
Change-Id: I5156eb97648927e5fe6e467abb8e3e055a231fec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-06src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685 Reviewed-by: David Guckian Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stdint.h>'Elyes HAOUAS
unused includes of <stdin.h> found using following commande: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\| uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\| u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\ |INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\ |INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/) |grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-04src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2adf28d805fe248d55a9514f74c38280c0ad9a78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-19arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHEKyösti Mälkki
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-19src: Remove unused 'include <arch/cpu.h>'Elyes HAOUAS
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19src: Use '#include <smp/node.h>' when appropriateElyes HAOUAS
Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-14bootblock: Provide some common prototypesKyösti Mälkki
The split of bootblock initialisation to cpu, northbridge and southbridge is not specific to intel at all, create new header <arch/bootblock.h> as AMD will want some of these too. Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-03cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-31cpu/x86: make set_msr_bit publicly availableMichael Niewöhner
Haswell and model_2065 implement a static set_msr_bit helper which should be publicly available instead. Move it to cpu/x86. Change-Id: I68b314c917f15fc6e5351de1c539d5a3ae646df8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36338 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-01cpu/intel/common: Move intel_ht_sibling() to common folderPatrick Rudolph
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-24cpu/intel: Use CPU_INTEL_COMMON_TIMEBASEKyösti Mälkki
Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-15cpu/intel/microcode: Make microcode lib available in bootblockRizwan Qureshi
Make microcode lib available in bootblock. Now that microcode.c is compiled in bootlock no need to include it explicitly, hence remove its references. Change-Id: I419da6af70222902e3ca39fc2133d5dc8558e053 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35278 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13intel/haswell: Remove some __PRE_RAM__ useKyösti Mälkki
Change-Id: I167e9a171af4fe7997ebb76cdfa22a4578817a55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35380 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I39f52764dc377c25953ef5dba16982a0b4637cdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/35181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-28intel/haswell: Use smm_subregion()Kyösti Mälkki
Change-Id: Idfb13ab03d4d4ae764bdda62a29848db9d8dcd81 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34737 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/haswell,broadwell: Rename EMRR to PRMRRKyösti Mälkki
The MSRs were already named as PRMRR in broadwell, just mismatching with the rest of the code. All later devices use the names PRMRR and UNCORE_PRMRR for these MSRs. Reflect the name change in structures and local variables. Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20devicetree: Remove duplicate chip_ops declarationsKyösti Mälkki
These are only referenced inside auto-generated static.c files, and util/sconfig also generates the declarations automatically from source file pathnames. Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki
Change-Id: I7176efdd1000789a093a1b4e243b4b150e6bb06f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34864 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13cpu/x86: Separate save_state struct headersKyösti Mälkki
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11intel/haswell: Move platform_enter_postcar()Kyösti Mälkki
Do this for consistency with remaining cpu/intel sources. Also wipe out some spurious includes. Change-Id: I1adde58966eae9205703b87e7aa17c50e5791a85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-03intel/haswell: Move stage_cache support functionKyösti Mälkki
Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE. Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-13intel/haswell: Replace monotonic timerKyösti Mälkki
Remove implementation of 24 MHz clock, available only on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead for all boards. Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-13cpu/x86: Move smm_lock() prototypeKyösti Mälkki
The function implementations are in local platform scopes. Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki
This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-04arch/x86: Adjust size of postcar stackKyösti Mälkki
With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient. The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-01Use 3rdparty/intel-microcodeArthur Heymans
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel. This allows for some finegrained control where family+model span multiple targets. Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products. The following MCU are get a new revision: old: sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552 sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528 sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288 sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312 sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728 sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384 sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336 sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280 sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304 sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432 sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328 new: sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552 sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504 sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288 sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336 sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728 sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408 sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360 sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304 sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328 sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456 sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352 Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-22src/cpu: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Change-Id: I44346594bc106eed73a1268b82f026b69e5f4512 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-21cpu: Add missing #include <commonlib/helpers.h>Elyes HAOUAS
ALIGN and ALIGN_UP needs 'helpers.h' Change-Id: Ib3a9e0d6caff69f4b0adb54364b47cc6ac52a610 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-21cpu/intel/haswell: Link monotonic_timer.c in early stagesArthur Heymans
This is needed for SPI flash console in bootblock/romstage/postcar. Change-Id: I18253cc028e87cd31879d722a6d788917e9c97b3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-21cpu/intel/haswell: Link tsc_freq.c in the bootblockArthur Heymans
This provides tsc_freq_mhz implementation. Change-Id: Ic6a84336f89a37aa412a9cc8c375fbd41dc09cf2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-21cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35Elyes HAOUAS
Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register name of the msr at 0x35 is MSR_CORE_THREAD_COUNT. Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33015 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-25cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZEArthur Heymans
CPU's featuring a non eviction mode cache the whole ROM. Therefore XIP stages don't need to follow some alignment constraints. Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-21nb/intel/haswell: Add an option for where verstage startsArthur Heymans
Previously Haswell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 14:18:52 +0000