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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-08 09:56:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-09 12:48:46 +0000
commit8abf66e4e06412db08918dcde31f2d515040a409 (patch)
tree42f13869f4a0da507452ea66f1bca9dad89f05cc /src/cpu/intel/haswell
parent4d372c7353727e9ffce9ec4e6b2de3cd6ab8e320 (diff)
cpu/x86: Flip SMM_TSEG default
This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/cpu/intel/haswell')
-rw-r--r--src/cpu/intel/haswell/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 5936953b52..9cc040ec62 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
- select SMM_TSEG
select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE