coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2014-08-12	cpu/intel/XXX/acpi.c: Fix coding style violation	Martin Roth
2014-08-04	cpu/intel: Fix out-of-bounds read due to off-by-one in condition	Edward O'Callaghan
2014-07-30	model_206ax_init.c: Trivial - fix indent	Edward O'Callaghan
2014-07-23	cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro `IS_ENABLED()`	Paul Menzel
2014-07-08	cpu: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-07-05	intel: Make monotonic timer a first class citizen	Edward O'Callaghan
2014-05-30	cpu/intel/fsp_model_206ax: change realpath to readlink	Martin Roth
2014-05-17	build: separate CPPFLAGS from CFLAGS	Patrick Georgi
2014-05-17	build: CPPFLAGS is more common than INCLUDES	Patrick Georgi
2014-05-10	Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT	Kyösti Mälkki
2014-05-09	cougar_canyon2: Switch CPU/NB/SB to the shared FSP code	Martin Roth
2014-05-06	Introduce stage-specific architecture for coreboot	Furquan Shaikh
2014-05-03	Move ARCH_* from board/Kconfig to cpu or soc Kconfig.	Furquan Shaikh
2014-04-26	Rename coreboot_ram stage to ramstage	Furquan Shaikh
2014-03-16	Make POST device configurable.	Idwer Vollering
2014-02-12	PCI: Drop includes under cpu	Kyösti Mälkki
2014-02-06	usbdebug: Drop obsolete code	Kyösti Mälkki
2014-01-15	Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR	Kyösti Mälkki
2014-01-11	intel/fsp: Fix microcode including	Patrick Georgi
2013-12-13	cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS	Alexandru Gagniuc
2013-12-05	cpu: Remove BOARD_MICROCODE_CBFS_GENERATE Kconfig option	Alexandru Gagniuc
2013-12-04	Add the Intel FSP 206ax CPU core support	Marc Jones