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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-06-27 12:13:30 +1000 |
|---|---|---|
| committer | David Hendricks <dhendrix@chromium.org> | 2014-07-05 00:38:06 +0200 |
| commit | ba92428514d8cac8045faa1dc573599424ef7231 (patch) | |
| tree | 53b7925af5863012b81994334bb9ef904cb57625 /src/cpu/intel/fsp_model_206ax | |
| parent | bda9a821142c0a105bc8892aef610ea43ce3400c (diff) | |
intel: Make monotonic timer a first class citizen
The monotonic time now needs to be a first class citizen in Coreboot as
it is a hard dependency of the drivers/spi flash command polling
function.
Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6135
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/fsp_model_206ax')
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 0fb4437cbd..043320cbe9 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string |