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path: root/src/arch/riscv
AgeCommit message (Expand)Author
2019-02-09riscv: Use correct argument in a1 when invoking payloadPhilipp Hug
2019-02-02riscv: Show hart id in trap handlerPhilipp Hug
2019-02-02riscv: Simplify payload handlingXiang Wang
2019-01-24riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCVRonald G. Minnich
2019-01-17riscv: create Kconfig architecture features for new partsRonald G. Minnich
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
2018-12-19arch/riscv: Don't set FPU state to "dirty"Jonathan Neuschäfer
2018-12-19arch/riscv: Define and use SBI_ENOSYSJonathan Neuschäfer
2018-12-18arch/riscv: Don't hardcode CSR numbers anymoreJonathan Neuschäfer
2018-12-07riscv: fix non-SMP supportPhilipp Hug
2018-11-19src: Add required space after "switch"Elyes HAOUAS
2018-11-05riscv: add support for supervisor binary interface (SBI)Xiang Wang
2018-11-05riscv: add support to block smp in each stageXiang Wang
2018-11-05riscv: add support smp_pause / smp_resumeXiang Wang
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-30riscv: simplify timer interrupt handlingPhilipp Hug
2018-10-30src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcodePhilipp Hug
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
2018-10-11riscv: add physical memory protection (PMP) supportXiang Wang
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-06arch/riscv: Update comment about mstatus initializationJonathan Neuschäfer
2018-10-04arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer
2018-09-26arch/riscv: Advance the PC after handling misaligned load/storeJonathan Neuschäfer
2018-09-21arch/riscv/include/arch: Don't use device_tElyes HAOUAS
2018-09-16riscv: don't write to mstatus.XSXiang Wang
2018-09-15arch/riscv: Configure delegation only if S-mode is supportedJonathan Neuschäfer
2018-09-14arch/riscv: Only execute on hart 0 for nowPhilipp Hug
2018-09-14arch/riscv: provide a monotonic timerPhilipp Hug
2018-09-14arch/riscv: add missing endian.h header to io.hPhilipp Hug
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
2018-09-10riscv: update misaligned memory access exception handlingXiang Wang
2018-09-10riscv: update mtime initializationXiang Wang
2018-09-05riscv: add entry assembly file for RAMSTAGEXiang Wang
2018-09-05riscv: add support to check machine length at runtimeXiang Wang
2018-09-04riscv: add spin lock supportXiang Wang
2018-09-04riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang
2018-09-02riscv: separately define stack locations at different stagesXiang Wang
2018-08-30riscv: update the definition of intptr_t/uintptr_tXiang Wang
2018-08-07arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner
2018-08-01riscv: remove redundancy in MakefileXiang Wang
2018-07-31riscv: fix issues (timestrap & PRIu64)Xiang Wang
2018-07-30riscv: delete src/arch/riscv/prologue.incXiang Wang
2018-07-18arch/riscv: Fix makefile to only set flags for riscvMartin Roth
2018-07-18riscv: add CAR interface Xiang Wang
2018-07-17riscv: add support for modifying compiler optionsXiang Wang
2018-07-12riscv: add include/arch/smp/ directoryXiang Wang
2018-07-11riscv: add support to check ISA extensionXiang Wang
2018-07-06riscv: use __riscv_atomic to check support A extensionXiang Wang
2018-04-27RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer
2018-04-26arch/riscv: Store mprv bit in size_tJonathan Neuschäfer
2018-04-11arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer
2018-02-20arch/riscv: Delegate the page fault exceptionsJonathan Neuschäfer
2018-02-20arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer
2018-02-20arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer
2018-02-20arch/riscv: Don't set up virtual memoryJonathan Neuschäfer
2018-02-20arch/riscv: Make RVC support configurableJonathan Neuschäfer
2018-02-20arch/riscv: Align trap_entry to 4 bytes, as required by specJonathan Neuschäfer
2017-12-02arch/riscv: Remove supervisor_trap_entryJonathan Neuschäfer
2017-12-02riscv: Remove config string supportJonathan Neuschäfer
2017-12-02arch/riscv: Remove the current SBI implementationJonathan Neuschäfer
2017-12-02arch/riscv: Return from trap_handler instead of jumping outJonathan Neuschäfer
2017-12-02arch/riscv: Unify trap returnJonathan Neuschäfer
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
2017-11-07arch/riscv: Use a separate trap stackJonathan Neuschäfer
2017-11-07arch/riscv: gettimer: Don't use the config stringJonathan Neuschäfer
2017-11-07arch/riscv: Drop mret workaroundJonathan Neuschäfer
2017-11-07arch/riscv: mprv_read_*: Mark result as earlyclobberJonathan Neuschäfer
2017-11-07arch/riscv: Fix return type of mprv_read_u64Jonathan Neuschäfer
2017-09-27arch/riscv: hls_init: Initialize time{,cmp} with dummy pointersJonathan Neuschäfer
2017-09-27arch/riscv: Document mprv_{read,write}_* functionsJonathan Neuschäfer
2017-09-27arch/riscv: trap handler: Print load/store access width in bitsJonathan Neuschäfer
2017-09-26riscv: Update register addresswxjstz
2017-07-25src/arch: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
2017-07-07arch/*: Update Kconfig symbol usageMartin Roth
2017-06-07src: change coreboot to lowercaseMartin Roth
2017-05-30arch: Unify basic cache clearing APIJulius Werner
2017-02-20riscv: Suppress invalid coverity errorsMartin Roth
2017-01-16riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer
2017-01-16riscv: get SBI calls to workRonald G. Minnich
2016-12-20riscv: enable counters via m[us]counterenRonald G. Minnich
2016-12-18riscv: Add support for timer interruptsRonald G. Minnich
2016-12-06riscv: Stub out sbi_(un)mask_interruptJonathan Neuschäfer
2016-12-06arch/riscv/mcall.c: Return the correct memory base and sizeJonathan Neuschäfer
2016-11-20riscv: map first 4GiB of physical address spaceRonald G. Minnich
2016-11-14riscv: add a variable to control trap managementRonald G. Minnich
2016-11-13riscv: change payload() to pass the config string pointer as arg0Ronald G. Minnich
2016-11-12riscv: start to use the configstring functionsRonald G. Minnich
2016-11-07riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer
2016-11-02riscv: Add a bandaid for the new toolchainRonald G. Minnich
2016-10-24RISCV: Clean up the common architectural codeRonald G. Minnich
2016-10-18arch/riscv: In trap handler, don't print SP twiceJonathan Neuschäfer
2016-10-15arch/riscv: Visually align trap frame informationJonathan Neuschäfer
2016-10-15riscv: Use the generic src/lib/bootblock.cJonathan Neuschäfer
2016-10-15arch/riscv: Remove unused bootblock_simple.cJonathan Neuschäfer
2016-10-15riscv: Clean up {qemu,spike}_utilJonathan Neuschäfer
2016-10-15riscv and power8: Convert printk/while(1) to dieJonathan Neuschäfer
2016-10-07RISCV: update the encoding.h file.Ronald G. Minnich
2016-09-12src/arch: Improve code formattingElyes HAOUAS
2016-08-29arch/riscv: Add missing "break;"Jonathan Neuschäfer
2016-08-23arch/riscv: Add functions to read/write memory on behalf of supervisor/user modeJonathan Neuschäfer