riscv: Unify SBI call implementations under arch/riscv/

Note that currently, traps are only handled by the trap handler
installed in the bootblock. The romstage and ramstage don't override it.

TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux
     payload. It worked as much as before (Linux didn't boot, but it
     made some successful SBI calls)

Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

4 files changed, 105 insertions, 4 deletions

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index cf6ce99fb0..1fe8f7c268 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -34,6 +34,7 @@ $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
 bootblock-y = bootblock.S stages.c
 bootblock-y += trap_util.S
 bootblock-y += trap_handler.c
+bootblock-y += mcall.c
 bootblock-y += virtual_memory.c
 bootblock-y += boot.c
 bootblock-y += misc.c
@@ -89,7 +90,6 @@ endif
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 
 ramstage-y =
-ramstage-y += trap_handler.c
 ramstage-y += virtual_memory.c
 ramstage-y += stages.c
 ramstage-y += misc.c
diff --git a/src/arch/riscv/include/spike_util.h b/src/arch/riscv/include/mcall.h
index 175ee6ce2f..a43b9cf49b 100644
--- a/src/arch/riscv/include/spike_util.h
+++ b/src/arch/riscv/include/mcall.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SPIKE_UTIL_H
-#define _SPIKE_UTIL_H
+#ifndef _MCALL_H
+#define _MCALL_H
 
 #include <arch/encoding.h>
 #include <atomic.h>
diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c
new file mode 100644
index 0000000000..fdc02bef2b
--- /dev/null
+++ b/src/arch/riscv/mcall.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2013, The Regents of the University of California (Regents).
+ * All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Regents nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+ * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+ * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+ */
+
+#include <arch/barrier.h>
+#include <arch/errno.h>
+#include <atomic.h>
+#include <console/console.h>
+#include <mcall.h>
+#include <string.h>
+#include <vm.h>
+
+uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info)
+{
+	if (id == 0) {
+		mprv_write_ulong(&info->base, 2U*GiB);
+
+		/* TODO: Return the correct value */
+		mprv_write_ulong(&info->size, 1*GiB);
+		return 0;
+	}
+
+	return -1;
+}
+
+uintptr_t mcall_send_ipi(uintptr_t recipient)
+{
+	die("mcall_send_ipi is currently not implemented");
+	return 0;
+}
+
+uintptr_t mcall_clear_ipi(void)
+{
+	// only clear SSIP if no other events are pending
+	if (HLS()->device_response_queue_head == NULL) {
+		clear_csr(mip, MIP_SSIP);
+		/* Ensure the other hart sees it. */
+		mb();
+	}
+
+	return atomic_swap(&HLS()->ipi_pending, 0);
+}
+
+uintptr_t mcall_shutdown(void)
+{
+	die("mcall_shutdown is currently not implemented");
+	return 0;
+}
+
+uintptr_t mcall_set_timer(unsigned long long when)
+{
+	printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n");
+	return 0;
+}
+
+uintptr_t mcall_dev_req(sbi_device_message *m)
+{
+	die("mcall_dev_req is currently not implemented");
+	return 0;
+}
+
+uintptr_t mcall_dev_resp(void)
+{
+	die("mcall_dev_resp is currently not implemented");
+	return 0;
+}
+
+void hls_init(uint32_t hart_id)
+{
+	memset(HLS(), 0, sizeof(*HLS()));
+	HLS()->hart_id = hart_id;
+}
+
+uintptr_t mcall_console_putchar(uint8_t ch)
+{
+	do_putchar(ch);
+	return 0;
+}
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 8c69366ba8..c7a11c6b9c 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -17,7 +17,7 @@
 #include <arch/exception.h>
 #include <arch/sbi.h>
 #include <console/console.h>
-#include <spike_util.h>
+#include <mcall.h>
 #include <string.h>
 #include <vm.h>