coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2024-03-14	arch/riscv: support physical memory protection (PMP) registers	Ronald G Minnich
2024-03-09	arch/riscv: Add SMP support for exception handler	Xiang Wang
2023-12-09	arch/riscv/payload: Remove old RISC-V CSR names	Lennart Eichhorn
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-03-06	src/arch/riscv: Convert to SPDX license header	Patrick Georgi
2019-08-03	riscv: add support for OpenSBI	Xiang Wang
2019-06-23	riscv: use mret to invoke M-mode payload and disable interrupts	Xiang Wang
2019-02-09	riscv: Use correct argument in a1 when invoking payload	Philipp Hug
2019-02-02	riscv: Simplify payload handling	Xiang Wang