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2021-03-04drivers/generic/max98357a: Use depends HAVE_ACPI_TABLESEric Lai
Replace if HAVE_ACPI_TABLES statement with depends HAVE_ACPI_TABLES. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie6ebfde49f0f3c205e174c5113feb75444dedba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-04drivers/generic/alc1015: add ALC1015 AMP driverEric Lai
Add ALC1015 AMP support. ALC1015Q-VB Datasheet Rev 0.1 BUG=b:177971830 TEST: ALC1015P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id93845024aa2cded69acc88d594c222f2f821f79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51051 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04mb/google/volteer/variants/copano: Describe USB ports in devicetreehao_chou
Modify USB port to match schematics. And assigned USB2 port to type-c use. BUG=b:177481079 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Change-Id: I25412d16df8ad809c05635022c11bd8882d002c5 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49980 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04soc/rockchip/rk3399/sdram: Add channel to error messageMoritz Fischer
When printing error information during DRAM training, be more verbose by printing the channel number. Change-Id: If4109bd0573e3d9f90d699d89350ddbcc48714d3 Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-04soc/rockchip/rk3399/sdram: Simplify error conditionMoritz Fischer
There is no need for explicit 0 comparison, any return value not equal to 0 is treated as error. Change-Id: I72612af4108a616b6247ee68c8ac2a53242b0853 Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-03vc/amd/fsp/picasso: increase FSPS UPD block size from 0x152 to 0x202Nikolai Vyssotski
We will need more FSPS UPD space for PEI GOP changes coming. BUG=b:171234996 BRANCH=Zork Cq-Depend: chrome-internal:3609213, chromium:50576 Change-Id: I35d0bb0ee30e04f66882b6103acd9d673d040c07 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-03amd_blobs: update submodule pointerNikolai Vyssotski
Pick up build 0x26 Picasso FSP binaries. The changes include increased FSPS UPD block size from 0x152 to 0x202. Change-Id: I11fc199ca7bc6ee7431c59d35a60d9ebd977bf10 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-03MAINTAINERS: Add Jakub as maintainer for tests/Patrick Georgi
He practically is, so let's make it official. Change-Id: I8adae5071f94ff309834fcab17b5a722e5c44b10 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com>
2021-03-03soc/amd/cezanne/chipset.cb: rename alias for SATA controllersFelix Held
Renoir/Cezanne have two SATA controllers with 2 ports each, so call them sata_0 and sata_1. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51190 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/google/zork/var/vilboz: Update WiFi SAR for VilbozFrank Wu
Loading wifi_sar-vilboz-1.hex for vilboz360 LTE sku for the present. BUG=b:177684735, b:176168400 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-03mb/amd/majolica: Add eSPI supportZheng Bao
Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-03mb/google/brya: Add support for 2 new DRAM partsAmanda Huang
1) Micron MT53E1G32D2NP-046 2) Micron MT53E2G32D4NQ-046 BUG=b:181378727 TEST=none Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03util: Add new memory part to LP4x listAmanda Huang
Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03mb/google/brya: fix BT enumeration issueAamir Bohra
Current implementation exposes GPP_F4 cnvi reset pin as reset gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven by SoC. It should not be driven by driver. BUG=b:180875586 Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/common/block/smbus: Add config to use ACPIMaxim Polyakov
Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44865 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel: Guard macro parameters in pm.hAngel Pons
Guard against unintended operator precedence and associativity issues. Change-Id: I342682a57fde9942cdf7be10756ee21c10af802a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50917 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/cannonlake: Move `gpi_clear_int_cfg()` callAngel Pons
To allow unifying bootblock.c in follow-ups, move a function call. Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03soc/intel: Factor out common smmrelocate.cAngel Pons
There are seven identical copies of the same file. One is enough. Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/skylake: Always print ME FW SKUBenjamin Doron
State of ME firmware SKU is independent of power-down mitigation. Change-Id: I014c1697213efaefcb0c2a193128a876ef905903 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03soc/intel/skylake: Enable compression on FSP-SBenjamin Doron
Use LZ4 algorithm to compress FSP-S. This saves ~40 KiB and reduces the boot time by ~7 ms. LZMA would save a further ~1 KiB, but adds ~9 ms to the boot time. LZMA size: fsps_lzma.bin 0xb0dc0 fsp 146578 LZMA (188416 decompressed) LZMA decompression time: 15:starting LZMA decompress (ignore for x86) 388,716 (47,646) 16:finished LZMA decompress (ignore for x86) 406,167 (17,450) LZ4 size: fsps_lz4.bin 0x242dc0 fsp 147442 LZ4 (188416 decompressed) LZ4 decompression time: 17:starting LZ4 decompress (ignore for x86) 384,736 (47,864) 18:finished LZ4 decompress (ignore for x86) 384,796 (59) Change-Id: Idace01227cfd2312b2c4c4ea1e6aaac8c21cd6b0 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-03soc/intel/alderlake: Log internal device wake eventsTim Wawrzynczak
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-03soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devicesTim Wawrzynczak
Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47413 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/alderlake: Add PCIe root port wake sources to elogTim Wawrzynczak
Log PCIe root port wake events in the elog. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-03sb/intel/lynxpoint/lpc.c: Relocate lock bit writeAngel Pons
This lock bit can be set later, and should also be set for LynxPoint-H. This eases merging with Broadwell, which already sets this lock bit after `spi_finalize_ops()` in a dedicated finalisation function. Tested on Asrock B85M Pro4 (LynxPoint-H), the lock bit is now set. Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03AGESA boards: Captilize ASL namesPaul Menzel
ASL+ Optimizing Compiler/Disassembler version 20200925 remarks: IASL build/dsdt.aml Intel ACPI Component Architecture ASL+ Optimizing Compiler/Disassembler version 20200925 Copyright (c) 2000 - 2020 Intel Corporation dsdt.asl 222: Name(PSa, Package(){ Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (PSA_) dsdt.asl 228: Name(APSa, Package(){ Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (APSA) Execute the command below to fix all occurences: git grep -l PSa | xargs sed -i 's/PSa/PSA/g' Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03configs/config.google_volteer.build_test_purposes: Add fileAngel Pons
This is meant to build-test Crashlog and various debug options. Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com>
2021-03-03soc/intel/tigerlake: Re-use existing define in CrashLog implementationFrancois Toguo
TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS. This fix re-uses an already existing variable in crashLog. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/purism/librem_mini: Implement `die_notify`Angel Pons
Make the SATA LED blink when coreboot dies. GPIO functions aren't compiled in for postcar, so add a check to prevent linker failures. TEST: Try to boot Librem Mini WHL without RAM, observe blinking (and also blinding LED). Re-install RAM (and re-seat RAM a few times), boot to OS, and observe SATA LED operating normally, as expected. Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50013 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/*/*: Don't select PCIEXP_HOTPLUGArthur Heymans
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced. Just change the default value to 'y'. Change-Id: Ie4248700f5ab5168bff551b740d347713273763c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03soc/intel: Backport SMRR locking supportAngel Pons
Backport commit 0cded1f116 (soc/intel/tigerlake: Add SMRR Locking support) to other client platforms. The SMRR MSRs are core-scoped on Skylake and Ice Lake, at least. Older platforms do not support SMRR locking, but now there's seven copies of the same file in the tree. A follow-up will deduplicate smmrelocate.c files into common CPU code. I cannot test Jasper Lake nor Elkhart Lake, but they should still work. As per documentation I do not have access to, Elkhart Lake seems to support SMRR locking. However, Jasper Lake documentation is unclear. Tested on Purism Librem Mini v1 (WHL-U i7-8565U), still boots and SMRR MSRs have the same value on all cores/threads (i7-8565U supports HT). Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-03mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG deviceArthur Heymans
Pineview does not support PEG. Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03mb/intel/d510mo/devicetree.cb: Indent with tabsArthur Heymans
This is a cosmetic change. Make the formatting consistent with the rest of the tree. Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03mb/gigabyte: Add GA-D510UDAngel Pons
Booted fine on the first try. Most things work properly, but I haven't tested them thoroughly. Native raminit chokes with a DIMM in the second slot, but the first slot works properly. Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-03lib/cbfs.c: Fix return value of failure to measureArthur Heymans
Returning an error on a failure to measure makes the system not bootable. Change-Id: Ifd20e543d3b30de045c0656eccdcc494c2fb10ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-03-03mb/google/dedede/var/drawcia: Re-tune override GPIO tableKarthikeyan Ramasubramanian
There is going to be an upcoming board version for Drawlat/man and Drawcia. Hence apply the override GPIO table without pad termination for board versions 6 or 8 alone. BUG=None BRANCH=dedede TEST=Build and boot to OS in Drawcia. Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-03mb/google/guybrush: Add SPDs to build for Guybrush variantMartin Roth
These files were automatically generated by the lpddr4 version of gen_part_id.go. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3797ba6d52248961418000614a4f7885182521a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03mb/google/guybrush: Add generated LPDDR4x SPDsMartin Roth
These SPDs were generated by the lpddr4 version of gen_spd.go from the global_lp4x_mem_parts.json.txt file. BUG=b:178715165 TEST=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03util/spd_tools/lp4x: Add 2 new parts to global memory definitionMartin Roth
This adds the definitions for MT53E1G32D4NQ-046 WT:E used on Majolica, and the NT6AP256T32AV-J1 part used on Guybrush. BUG=b:178715165 TEST=Generate SPDs Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-02google/trogdor: Fix trogdor-rev1 eDP power GPIOJulius Werner
Looks like I forgot about trogdor-rev1 in CB:51004. Unlike rev0 (other special case) or rev2 (works like CoachZ/Homestar), rev1 used the same pin as Lazor and Pompom for EN_PP3300_DX_EDP. Apparently there are still some people using these, so add in another special case for that. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7093aa63778d69fde240af3b0c62b97ac99c28dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51196 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02soc/amd/cezanne: Disable legacy DMA IO portsRaul E Rangel
The legacy DMA is not used by linux. This change frees up those IO ports. When FSP-S runs, it re-enables the legacy DMA IO region, so we need to disable it again. BOOTBLOCK: PMx00: 0xe3060bf3 ROMSTAGE - Before FSP: PMx00: 0xe3060bf3 ROMSTAGE - After FSP: PMx00: 0xe3060bf7 BUG=b:180949454 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51076 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/amd/majolica: Enable required devices in devicetreeMathew King
Most devices are now disabled by default in the chipset. Enable the iGPU and two XHCI controllers that are required to boot the board. BUG=b:180528708 TEST=To be tested Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I54a4547217fb8e9f67fc0c8e1e36e96dfaae331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51095 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/guybrush: Set up FW_CONFIG fieldsMathew King
BUG=b:180523962 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-02mb/google/guybrush: Add eSPI configurationMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic607d6bca5c70255332a6fbee2b63e6daba7d1e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51047 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02tests: Add lib/compute_ip_checksum-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I61c578ec93837cb2581a1ab9e2f3db2a0dd69f3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-02tests: Add lib/crc_byte-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I9016cd7825cb681fd200b23dd362ca24acf69192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-02soc/amd/cezanne: Fill out pci devices in chipset.cbMathew King
BUG=b:180528708 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Iecc75afd7a914651ca15b811163d3559bf73ac9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-02mb/google/brya: Fix a few mistakes in brya0 overridetreeTim Wawrzynczak
1) Both SAR sensors had a UID of `2`, making them indistinguishable 2) No `device` underneath max98357a `chip` Change-Id: Icf586229532819a7779652cbee73755b036dfbdc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02soc/amd/common/blocks/lpc: Explicitly disable serial IRQRaul E Rangel
The serirq enable bit defaults to true, so if we want it disabled, we need to explicitly disable it. BUG=b:180631748 TEST=Boot majolica and see spurious IRQ 9 gone. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-02mb/lenovo/x200: Fix docking eventsNico Huber
Even though `device` entries are children of `chip` entries in the devicetree source format, the chips in the translated C structures are only hooked up to device nodes. Hence, to configure a chip in a device- or overridetree, it always needs a `device` below it. This should fix docking events for the X200 ThinkPad. Change-Id: I561e7ae81f2e096a091868ce51daa1c8f66af067 Signed-off-by: Nico Huber <nico.h@gmx.de> Found-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kevin Keijzer Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-02mb/google/guybrush: Add option to toggle GPIO for sign of lifeMathew King
Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing. BUG=b:180721202 TEST=builds Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-01soc/intel/skylake: Move `gspi_early_bar_init()` callAngel Pons
For consistency with newer platforms, do this in pch.c instead. Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-01soc/intel: Drop `bootblock_cpu_init()` functionAngel Pons
Just call `fast_spi_cache_bios_region()` directly instead. Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/cannonlake: Drop unnecessary guardAngel Pons
The MRC cache driver assumes BOOT_DEVICE_MEMORY_MAPPED=y already. This is to ease factoring out common code across seven Intel platforms. Change-Id: I0598cb18b456e10789b2a42792fbfa2639cdd2c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50951 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/{skl,cnl}: Do not chain-include systemagent.hAngel Pons
Change-Id: I8f48765ad99dad49f9d94c45aa4af6aff2ed702c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50950 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01skylake,fsp1_1: Delete dead `report_memory_config()` functionAngel Pons
RAM is not yet configured in bootblock. This function was copy-pasted from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in there can be removed as nothing else uses them. Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Extract fsp_params.c out of romstage.cAngel Pons
Done for consistency with newer platforms. Also clean up includes. Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50948 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Drop `romstage_pch_init()` functionAngel Pons
It only calls `smbus_common_init()`, so just call that directly. Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/{skl,icl}: Move tco_configure() to bootblockAngel Pons
Backport commit 03ed5bff5c (soc/intel/cannonlake: Move tco_configure to bootblock), commit bb50c67227 (soc/intel/tigerlake: Move tco_configure to bootblock) and commit 60c619f6a3 (soc/intel/jasperlake: Move tco_configure to bootblock) to other platforms. This is for consistency. Change-Id: I31fd0ceb67eacf30aefa457d757bf0d7f4cd7e87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/icelake: Rename `pch_init()` functionAngel Pons
There's two instances of the same function, one for the bootblock and another for romstage. Prefix them with the stage they are executed in. Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Drop unused function prototypesAngel Pons
Change-Id: I1b08b31876d6c10ac155fd67d4a505e8c272a15c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50943 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common smbus.hAngel Pons
Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definitionAngel Pons
According to document 332691-003EN (SPT-H datasheet volume 2), the hardware defaults to 0x44, which matches what newer platforms use. Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common gpe.hAngel Pons
The definitions are identical across seven platforms. Unify them. Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Move soc_acpi_name()Angel Pons
Done for consistency with newer platforms. Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50939 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out identical acpigen GPIO helpersAngel Pons
Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Clean up SD GPIO handlingAngel Pons
This is to align with newer platforms. Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Remove unused macro in cpu.hAngel Pons
Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50962 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Include gfx.asl from northbridgeAngel Pons
The iGPU is on the northbridge or system agent, not the southbridge. Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-01mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHzKane Chen
Modify I2C3 setting to follow I2C specification (lower than 400kHz). Original setting: .rise_time_ns = 184 .fall_time_ns = 42 Change to: .rise_time_ns = 110 .fall_time_ns = 34 BUG=b:181091107 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-01nb/intel/sandybridge: Clean up `dram_timing` functionAngel Pons
Compute timings first, then display them. Drop unneeded comments, too. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45501 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01tests: Add lib/memmove-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ic9b68eb0fa85bbc3f66d57cdcb329073b26bea57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-01sb/intel/bd82x6x: Turn ME PCI register structs into unionsAngel Pons
This allows dropping the `pci_read_dword_ptr` and `pci_write_dword_ptr` wrappers. Change-Id: I7a6916e535fbba9f05451d5302261418f950be83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49993 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01amd_blobs: Update cezanne PSP Secure OSMarshall Dawson
Avoid a Secure OS Abort. This prevents coreboot timing out on C2P mailbox commands and allows HDT unlocking. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I358530a1ba959ee1896e26a47853c9918ee124b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-01soc/amd/cezanne: Add PSP whitelist debug unlock supportRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/51078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01amd_blobs: Add cezanne whitelist bootloaderMarshall Dawson
Advance the pointer to pick up the PSP whitelist bootloader. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I45da509ee6f782cbe64e7099f3945129282060b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-01nb/intel/haswell: Fix DPR size handlingTim Wawrzynczak
DPR register's size field is given in whole MiB, so correct where it is used to ensure the correct size multiple (KiB vs. MiB) is used with it. Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling") Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01acpi: Move PCI functions to separate fileTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/common/gpio: Add gpio_routes_ioapic_irq functionTim Wawrzynczak
This function returns true if any GPIO pad is programmed to route the given IRQ to the IO-APIC. It does so by keeping track of which pads are routed to IOxAPIC and looking this up in the new function. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-01sb/intel/lynxpoint/me_9.x.c: Rename to me.cAngel Pons
This code will eventually support both ME 9.x and ME 10. Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-01nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflowAngel Pons
The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide. Clamp any values that would overflow this field. Bits in TC_DTP already get set when the tXP and/or tXPDLL values are large. Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/broadwell: Use ctdp.asl from HaswellAngel Pons
Both files are equivalent. Drop Broadwell's ctdp.asl and use Haswell's. Change-Id: Ida17d030d6022af18078321ee76b425095fe9f5c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-01mb/: Drop print of MAINBOARD_PART_NUMBERKyösti Mälkki
Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-01mb/ocp/deltalake: Fill ECC type in romstageAngel Pons
Fill the ECC type in `struct memory_info` in romstage, and in SoC code. The SMBIOS override is unnecessary, and this is not mainboard-specific. Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01memory_info.h: Store SMBIOS error correction typeAngel Pons
There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/amd/common/block/acpimmio: Add fch_disable_legacy_dma_ioRaul E Rangel
Add a method to disable decoding the legacy DMA IO ports. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51075 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01mb/google/dedede/var/sasukette: Configure I2C times for touchpad/codec/AMPTao Xia
Configure I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). Measured I2C frequency just as below after tuning: touchpad:372 kHz audio codec RT5682:386.8 kHz speaker AMP L:387.5 kHz speaker AMP R:388.9 kHz BUG=b:181342340 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I05d78c088190e349281a34b2aeed39ae8d867dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51112 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01mb/google/dedede/var/storo: Enable ELAN touchscreenchenzanxi
Add ELAN touchscreen into devicetree for storo. BUG=b:177389448 BRANCH=dedede TEST=built storo firmware and verified touchscreen function Change-Id: I0d9e5005928c6fda3d1f0ce8bd9ae135e4a04867 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50981 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27crossgcc: Delete conflicting, stale symbolic linkNico Huber
If a previous build failed or the build dir is still around for other reasons (e.g. buildgcc's `-t`) the symbolic link to our `bin` dir we create there is also still around and can't be created again without removing it first. Attempts to use `ln -f` also fail as the existing destination is treated as directory and a new symbolic link would be created inside. Change-Id: I7a2720b0286e33d1ba26ea01f323dbf4f8afaea0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27drivers/soundwire/alc1308 : Add ALC1308 soundwire deviceAnil Kumar
This patch adds new soundwire device ALC1308 The codec properties are filled out as best as possible with the datasheet as a reference. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. The unique ID is calculated from schematics by referring to ASEL[1:0] strap settings. Datasheet of ALC1308 provides info about the mapping of ASEL strap settings to unique ID For example this device is connected to master link ID 1 and has strap settings configuring it for unique ID 2. chip drivers/soundwire/alc1308 register "desc" = ""Left Speaker"" device generic 1.2 on end end Bug=None Test=Build and boot on TGLRVP.Extract SSDT and confirm that the entries for PCI0.HDAS.SNDW are present for ALC1308 Test speaker out functionality Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ibf3f1d5c6881cbd106e96ad1ff17ca216aa272ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/51042 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27mb/google/dedede/var/kracko: Add elan touchscreen supportTony Huang
BUG=b:177834652 BRANCH=dedede TEST=build kracko firmware Change-Id: I360920f80f4ce5dcbcde25c433e23803fa72569b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-27mb/intel/shadowmountain: Add the ASL codeV Sowmya
This reverts commit d510b60f5b4eee6c165039be4acbe89ff25d8a4a. This patch includes the DSDT ASL code for shadowmountain board. BUG=b:175808146 TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27mb/intel/shadowmountain: Add the ramstage codeV Sowmya
This patch includes the ramstage changes for the shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27arch/x86/smbios: Update SMBIOS type 17 asset tagTim Chu
Add SMBIOS type 17 asset tag. Use dimm locator as default value. Tested=Execute "dmidecode -t 17" to check asset tag field is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I323e6b4cf6b11ede253d5a2a4bfc976a3f432b05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27soc/intel/denverton_ns: Drop `pcidev_path_on_root_debug` usageAngel Pons
Currently, this function is only invoked for the SPI device through common SoC code. Since both Intel Harcuvar and Scaleway Tagada have enabled the SPI device in the devicetree, there's no need to use the debug version of `pcidev_path_on_root`. Change-Id: I4340d5860d23c2fa230105f7a7d345c367b2b2aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50128 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27Revert "util/lint: Add test for documentation in util dirs"Nico Huber
This reverts commit 15e379aaf334e7931710b4208ccedf2f9ee44b0d. It triggers on directories that only contain artifacts and no checked in code. As this happens a lot when switching branches, it makes it impossible to commit new code. Change-Id: I38a86c8a5d5dc14ca5f6cba789bcb8c0fcaefb0b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27nb/intel/ironlake: Avoid casting pointers to structsAngel Pons
Instead, convert the struct to a union and pass in a pointer to it. Tested on out-of-tree HP ProBook 6550b, still boots. Change-Id: I60e3dca7ad101d840759bdc0c88c50d9f07d65e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45367 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27nb/intel/ironlake: Handle broken ME firmwareAngel Pons
This allows booting without ME firmware, even though the 30-minute auto-shutdown still happens. Without this patch, an HP ProBook 6550b cannot get past the `setup_heci_uma` function call. Change-Id: I446c02ac6034ede75cb873a2e676c40e4ef84b7c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-27sb/intel/ibexpeak: Drop useless bd82x6x pcie.cAngel Pons
The PCIe device IDs for Ibexpeak are not in bd82x6x's pcie.c driver. Thus, the code has always been dead code on Ibexpeak. Drop it. Change-Id: Ide2b4af2a187ecf98f39a9c979646a7ed959c74f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51067 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27sb/intel/ibexpeak: Add all PCI IDs for LPCAngel Pons
Taken from document 322170-028 (5 series specification update). Tested on out-of-tree HP ProBook 6550b (HM57), fixes several issues. Without this patch, EHCI controllers had no IRQ assigned and there were unexpected exceptions about NMIs. With this patch, the issues are gone. Change-Id: Icd31dd89ba49e38a5e4c108a8361dbf636332ab8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51066 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 02:48:02 +0000