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2022-11-27mb/amd/mayan: Add framework for morgana crb mayanRitul Guru
mayan is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. amd/mayan is started as a copy of amd/birman. Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70010 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-26mb/google/brya/var/marasov: Update gpio tableFrank Chu
Based on latest schematic to update the gpio table. BUG=b:254365935 BRANCH=firmware-brya-14505.B TEST=FW_NAME=marasov emerge-brya coreboot Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I03b443826d39182eaf23ad3e4e0ba8d6b8a93022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69180 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-26mb/google/rex: Disable SATA from the devicetreeKapil Porwal
SATA is not supported on google/rex hence disable it. BUG=none TEST=Build and boot to google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I35a742ab9782feed86c3af514505d870d181b34b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.hSaurabh Mishra
Fix compilation issue due to enum macro redefinition by safeguarding definitions with DISPLAY_FSP_VERSION_INFO_2 in SoC Kconfig. Back-ported from commit f7e8adac7b3123 ("edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h") to fix compilation issue due to enum macro redefinition. BUG=b:260183604 TEST=Verify MTL Rex0 build with the patch and verify the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/69961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2022-11-26src/soc/intel: Remove unnecessary space after castsElyes Haouas
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26mb/google/nissa/var/craask: Add support for NVMeReka Norman
Enable NVMe GPIOs based on fw_config and add NVMe to devicetree. Note, eMMC and NVMe are not probed in devicetree. On first boot in factory, the device needs to boot with unprovisioned fw_config, so all storage devices should be enabled when unprovisioned. Currently, devicetree disables all probed devices when unprovisioned. If we want eMMC and NVMe to be probed, support needs to be added for enabling probed devices when unprovisioned. BUG=b:259211172 TEST=Verified by ODM. On craask, LTE and WCAM still work. On craaskneto, eMMC and NVMe SKUs can both boot. Change-Id: I76a056cddff2246cfb5bb26ddbdfc333b49d9aaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/69958 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-26soc/intel/meteorlake: Refactor heci finalize functionsSubrata Banik
This patch creates a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again FSP config. Currently, `heci_set_to_d0i3()` function is getting called twice. BUG=b:260041679 TEST=Able to build google/rex with this patch and observe coreboot log modification as below: Without this patch: [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] Finalizing chipset. [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 29 / 78 ms With this patch: [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] Finalizing chipset. [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 28 / 52 ms Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-26soc/intel/alderlake: Use common code CSE-Lite API for WP informationSubrata Banik
This patch drops the local implementation `log_me_ro_write_protection_info` and adopts the API from IA common code (cse_lite.c). BUG=none TEST=Able to compile the cse_lite.c file for google/kano without any error. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69969 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-26soc/intel/cmn/cse: Create API to get CSE Lite WP InformationSubrata Banik
This patch creates an API for CSE-Lite specific SKU to retrieve the Write Protect (WP) information (`cse_log_ro_write_protection_info`) like WP range and limit, if the region is write-protected or not etc. BUG=none TEST=Able to compile the cse_lite.c file for google/kano without any error. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-263rdparty/libgfxinit: Update submodule pointer to 066e52eeaa32Felix Singer
Change-Id: I9b36a4b5f0a7a075ddef5d4bec984f3cd131626d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-263rdparty/libhwbase: Update submodule pointer to 8be5a82b85ceFelix Singer
Change-Id: I5ad61c39125b19922ae2fdda9767544d857139d0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-26Update arm-trusted-firmware submodule to upstream v2.8.0Elyes Haouas
Updating from commit id 61fe7826d: 2022-10-18 16:20:05 +0200 - (Merge "feat(fvp): build delegated attestation in BL31" into integration) to commit id 9881bb93a: 2022-11-21 19:12:00 +0100 - (Merge "docs(spm): update threat model" into integration) This brings in 227 new commits. Change-Id: I6c902a7360b5436df22c829c7e387457598c3b94 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-25mb/google/nissa/var/xivu: Update DPTF parametersIan Feng
Follow thermal table from thermal team. 1. Modify TS1 passive policy to 68. BUG=b:249446156 TEST=emerge-nissa coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69960 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25mb/siemens/mc_ehl2: Disable L1 prefetcherMario Scheithauer
As for mainboard mc_ehl1, a hard real-time dependency is also required for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: I07b27dd672533e693a6c2987d16f54333850760e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-25cpu/intel/model_2065x: Don't use a magic APICArthur Heymans
Move the chip configuration to the cpu cluster device. It looks like none of the devicetree were featuring a lapic 0xacac, nor was tcc_offset ever set, so this remains a NOP. Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59315 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-25ACPI: Flag boards with ACPI_NO_MADTKyösti Mälkki
These boards do no fill MADT with useful information. Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69777 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25cpu/intel/haswell: Move chip_ops to cpu clusterArthur Heymans
The cpu cluster is always present and it's the proper device to contain the settings that need to be applied to all cpus. This makes it possible to remove the fake lapic from devicetrees. Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-25ACPI MADT: Add LINT1 as NMI sourceKyösti Mälkki
Set of boards and platforms did not have LINT1 configured as NMI source. Change-Id: I65044125562bda363b3a0d92da6137c77a28b587 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69528 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25ACPI: Use common code for MADT LAPIC NMIsKyösti Mälkki
Use the broadcast ID to deliver LINT1 as NMI to all CPUs, instead of listing individual LAPIC IDs. Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25{drivers/wifi, mb/google}: Rename `is_untrusted` to `add_acpi_dma_property`Kapil Porwal
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:259716145 TEST=Verified that the _DSD object is still present in the SSDT. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69937 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25util/testing: Fully clean all but the standard GCC buildMartin Roth
We don't currently use the artifacts from the Clang or CrOS GCC builds, so don't bother saving them. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I69fe803e4b4213a199d0b76089da443aa769aa92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-25soc/intel/adl/acpi: add FSPI to DSDTEran Mitrani
A previous CL ("Add missing ACPI device path names", commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors from the Kernel on Brya devices (see Tim's comment on patchset 8): > ACPI Error: AE_NOT_FOUND, While resolving a named reference > package element - \_SB_.PCI0.FSPI FSPI is defined in src/soc/intel/alderlake/chipset.cb: device pci 1f.5 alias fast_spi on end This CL adds the corresponding FSPI device to the DSDT to prevent the error mentioned above. TEST=Built and tested on brya by verifying the error is gone. BUG=b:231582182 Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69920 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25commonlib/fsp_relocate.c: Fix cbfstool build on 32-bit hostWerner Zeh
On a 32-bit host, uintptr_t is defined as 'unsigned int' instead of 'unsigend long int' like on a 64-bit host. When cbfstool is built on a 32-bit host, the printk format specifier '%lx' expects a 'long int' while new_addr is of type 'uintptr_t', aka 'unsigned int'. This in the end leads to a build error. To fix this and make it build on both, 32- and 64-bit hosts, use PRIxPTR as the format specifier. This macro will be resolved at compile time in the right way on both, 32- and 64-bit hosts. Test=Build cbfstool on 32- and 64-bit hosts. Change-Id: Ia917d2ed31778f3a29c0a6c7368f74c15319b099 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69682 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25crossgcc: Upgrade IASL from 20220331 to 20221020Elyes Haouas
Changes: https://acpica.org/node/201 Change-Id: I386a6757a318336bc616091afe0c4ed88cd89583 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-25drivers/intel/mipi_camera: Remove IPU ES support entry for RPLjimlai
The current IPU ES entry value is always set to true for RPL and kernel picks the ES version of the main IPU FW even for the production bootloader but loading is not successful due to the authentication failure. On Raptor Lake silicon, the production binaries are backward compatible with ES parts. This change removes the IPU ES support ACPI entry since the kernel needs to load the production IPU main firmware on both the ES/QS parts. BUG=b:258125833 TEST=Verify the Camera functionality by enabling the IPU secure mode on RPL variants with both ES/QS silicon. Signed-off-by: Jim Lai <jim.lai@intel.com> Change-Id: I9fd8ea0dd6ffdb16961bb017ba4388bf99e4d5bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/69929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-25crossgcc: Upgrade MPFR from 4.1.0 to 4.1.1Elyes Haouas
Change-Id: I7679c6751fb02ab670ade923b365c6410a6dc118 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-11-24util/lint: Ignore fmd files when evaluating Kconfig symbolsMartin Roth
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I5e3ff8ee10fdd3514033e72bd0c2664a4b2f5310 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-24mb/system76: Reset Realtek codec before configuringTim Crawford
Perform a codec reset before configuring to avoid potential issues like oryp5 had before 86f410479ca9 ("mb/system76/oryp5: Reset HDA before configuring"). Inspecting proprietary firmware for multiple boards shows that this is always done as well. Change-Id: I64c1fd23f708f77a81fad0bc889f42d4df3f6e61 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66918 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-11-24drivers/wwan/fm: Use correct GUID for DmaProperty in ACPI _DSDKapil Porwal
Use correct GUID for DmaProperty in ACPI _DSD. Reference: https://learn.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports Before: Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "DmaProperty", One } } }) After: Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) BUG=b:259716145 TEST=Verified the new GUID is reflected in ACPI SSDT at runtime. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I05b8c3bf23cc43863527bc514d9a96096d45003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69932 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-24google/*/*/sdram_configs.c: Add function argumentArthur Heymans
A function declaration without a prototype is deprecated in all versions of C. Change-Id: Ie22231908233f2fba25d78f6c5f53940011e8158 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69748 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24soc/amd: Define post codesMartin Roth
For the most part, this doesn't change any post codes, simply making the existing post-codes into macros. picasso/romstage.c did get a couple of post codes removed to match the other files. The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global at some point, while the POST_AGESA and POST_PSP codes would stay AMD specific. Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-24arch/arm: Use unified assembly syntaxArthur Heymans
Taken from Linux which also updated these files. Clang only works with this syntax, so this fixes builds for arm. TESTED on qemu vexpress-a9 and verstage on google/vilboz with BUILD_TIMELESS=1, binaries remain the same. Change-Id: Ia320dc2c460c99d934b8f17dee7748a9def4e750 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63058 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/google/brya/var/marasov: update pch_espi settingFrank Chu
Add conn0/conn1 for pch_espi. BUG=b:254365935 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I5969d2941c02400788d66521680fcd13d3a6b13f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69785 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24soc/intel/meteorlake: Decouple HECI disabling interface from its KconfigSubrata Banik
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG recommends to disable the CSE PCI device while CSE is in software temporary disable state. BUG=b:260183610 TEST=Able to build google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3c9c5a73028cde90af3553093a13d0c05b831bae Reviewed-on: https://review.coreboot.org/c/coreboot/+/69930 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/google/brya/var/marasov: Add touchscreen and touchpad for marasovFrank Chu
Declare touchscreen and touchpad under I2C3 and I2C5 BUG=b:254365935 BRANCH=firmware-brya-14505.B TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ifc865fc0c0c42af0d74272289c562e347fac3a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69467 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24lint/checkpatch: Add XA_STATE and XA_STATE_ORDER to the macro declarationElyes Haouas
This reduce the difference with linux v6.0-rc3. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ica20264d744ea8f77b56c63d29e1fafc2e68a869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-24sb/intel/i82801gx: Move SPIBASE and SPIBARxx to i82801gx.hElyes Haouas
Also remove unused DEBUG_PERIODIC_SMIS macro. Change-Id: Ieb8487c7757b89a09c1cee4a83f94b9077dac87e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-24sb/intel/i82801gx: Use "sb/intel/common/tco.h" macrosElyes Haouas
Also, use {read,write}_pmbase16() in lpc.c file instead of inw/out. Change-Id: Id281a3478051c4876ccbe26452d8744769c86654 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69878 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/siemens/mc_ehl2: Enable downshift for Marvell PHYsMario Scheithauer
Set downshift counter to 2 for all Marvell PHYs on this mainboard before the PHY downshifts to the next highest speed. Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24drivers/net/phy/m88e1512: Add downshift enableMario Scheithauer
This patch provides the functionality to enable downshift on Marvell PHY. By setting a downshift counter, the PHY is correspondingly often attempted to establish Gigabit link before the PHY downshifts to the next highest speed. The range is limited to 8 trials. To activate downshift, a software reset must follow to take effect. Change-Id: I4224eab6c1fc13824d53556c80435bc130a13bdb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69853 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/siemens/mc_ehl2: Enable Marvell PHY interruptMario Scheithauer
On this mainboard Marvell PHY INTn is routed to LED[2] pin. Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69434 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24drivers/net/phy/m88e1512: Add interrupt enableMario Scheithauer
INTn on Marvell PHY can be routed to LED[2] pin. This setting must be made via LED Timer Control Register on page 3. Change-Id: Ida1efbb604c382676b9d13ac8bf14de768f93637 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69433 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driverMario Scheithauer
This mainboard has three Marvel PHYs connected to the internal SOC GbE controllers. The default LED status after HW reset of this PHYs shows a different mode than what is needed. LED[2] is not connected on this mainboard. This patch sets the following LED status: LED[0] - 7 = On - 1000 Mbps Link, Off - Else LED[1] - 1 = On - Link, Blink - Activity, Off - No Link LED[2] - not connected TEST=Try different register values to verify LED feature. Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69387 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24drivers/net/phy/m88e1512: Provide functionality to customize LED statusMario Scheithauer
For Marvel PHY it could be necessary to customize the shown LED status at the connector. The LED status can be changed via Function Control Register on page 3. Link to the Marvell PHY 88E1512 datasheet: https://web.archive.org/web/20221109080111/https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-phys-transceivers-alaska-88e151x-datasheet.pdf Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24device/mdio: Provide helper functions for read and writeWerner Zeh
This patch provides helper functions to read or write a register via the MDIO bus. They can be used from drivers to easily access registers on the MDIO bus. Change-Id: I293d93435d27269a071b4b9b94a1b55307c575a7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69611 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24drivers/net/phy/m88e1512: Add new driver for Marvell PHY 88E1512Mario Scheithauer
This driver enables the usage of an external Marvell PHY 88E1512 which should be connected to a SOC internal MAC controller. In a first step it is only the framework of the driver. Functionality will follow with a second patch. Change-Id: I24011860caa7bb206770f9779eb34b689293db10 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69384 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24soc/intel/ehl: Add MDIO operation to TSN GbE deviceMario Scheithauer
This patch refactors the MDIO access for the TSN GbE device by placing the MDIO read and write functions into mdio_bus_operations struct which is assigned to the .ops_mdio member of the PCI device struct. In this way the MDIO interface of the TSN GbE device is exposed and can be used by other drivers if needed. Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-24src/device + util/sconfig: Introduce new device 'mdio'Mario Scheithauer
This patch extends the available device paths with a new device 'mdio'. MDIO is the 'Management Data Input/Output' called interface which is used to access an Ethernet PHY behind a MAC to change settings. The real payload data path is not handled by this interface. To address the PHY correctly on the MDIO bus, there is a 5 bit address needed, which often can be configured via pins on the mainboard. Therefore, the new introduced device has an 'addr' field to define its address. If one wants to use a MDIO device in devicetree, the syntax is straight forward (example): device mdio 0x2 on end As the MDIO interface is driven by the MAC, most likely this MDIO device will be hooked in as a child device of the (PCI attached) MAC device. With the new introduced ops_mdio a new interface is added to provide an API for read and write access over MDIO. Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69382 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24soc/intel/meteorlake: Skip setting D0I3 bit for HECI devicesKapil Porwal
This patch skips setting D0I3 bit for all HECI devices by FSP. The learning being made from Alder Lake platform showed that the CSE EOP cmd response time is highly nondeterministic and letting the EOP cmd issued by FSP makes the response time even worse. The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute (late sending of EOP) to ensure there is ample time for CSE to come to a state where the response to the EOP is almost immediate. There were a number of refactoring being done to ensure the EOP cmd can be sent at the later stage. #1: Ensure FSP is not putting those HECI devices into the D0i3. (SoC specific change) #2: Modify the CSE related boot state based operation to allow a proper window for sending late EOP cmd. (Common Code Specific change) The entire refactoring helps us to save ~60ms of boot time. Without those code change EOP sending timestamp as below: 943:after sending EOP to ME 1,248,328(61,954)) With those code change EOP sending timestamp as below: 943:after sending EOP to ME 1,231,660 (2,754) Port of commit d6da4ef69e4e ("soc/intel/alderlake: Skip setting D0I3 bit for HECI devices") to incorporate the #1 which is a SoC specific code change. BUG=none TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is set to `1`. Excerpt from google/rex coreboot log: [SPEW ] DisableD0I3SettingForHeci : 0x1 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-24mb/google/brya/var/marasov: Update SPD ID assignmentFrank Chu
Adjust SPD ID order DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 1 (0001) MT62F1G32D4DR-031 WT:B 2 (0010) H9JCNNNCP3MLYR-N6E 3 (0011) BUG=b:254365935 BRANCH=None TEST=run part_id_gen to generate SPD id Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I3a62cf355508debce387c48d9d089e73763b2bf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69784 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/google/rex: Adding cros_gpios to rexIvy Jian
Adding cros_gpios for crossystem to access WP GPIO BUG=b:258048687 TEST= run FAFT firmware_WriteProtect passed. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ieac1df805c6399aefdc13aae136630d496aacd58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69924 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/google/brask/variants/brask: remove fan settingZhuohao Lee
The brask doesn't include a real chassis so we don't need to configure the fan setting in the overridetree.cb. Instead, we can leave the fan running at full speed after the device boot up. BUG=b:259643676 BRANCH=firmware-brya-14505.B TEST=flashed the bios to the device and make sure the fan spinned at full speed. Change-Id: I6075b6171ca4d7b907679efd0ce7e355759385bc Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-23mb/google/brya/var/gladios: Update gpio tableKevin Chiu
Based on the latest schematic to update the gpio table. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ifaf0629dcd77d21cf09fe84e760f1f22c075467f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-23mb/google/brya/var/gaelin: Configure devicetree settingsRaymond Chung
Override devicetree configuration based on the latest gaelin schematic. BUG=b:249000573, b:254375472 BRANCH=firmware-brya-14505.B TEST=FW_NAME=emerge-brask coreboot Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-23mb/google/brya/var/gladios: Update devicetree settingKevin Chiu
Update devicetree setting per the schematic. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I8746d44daa43c06723bdfcac6803eb90a3c124b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-23soc/amd/*/fsp_m_params: rework local USB PHY table updateFelix Held
Update the fields that need to be updated directly in the local static usb_phy_config struct instead of dereferencing the pointer written to the corresponding UPD field. This will allow updating the type of UPD field in a follow-up commit to enable 64 bit coreboot builds. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69896 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-23soc/amd/*/Makefile: fix readelf parameters to get bootblock sizeFelix Held
This ports forward part of commit df0968062622 ("soc/amd/picasso: Add support for 64bit builds") to the newer AMD SoCs. Use -Wl instead of -l to get the output format that the commands in the Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this change, readelf will split the output into two lines in case of a 64 bit coreboot build. This results in invalid amdcompress and amdfwtool command lines which will cause the amdfwtool call to fail with Error: BIOS binary destination and uncompressed size are required With the old readelf -l command we get this output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000 0x0000000000010000 0x0000000000010000 RWE 0x10 while we get the correct output in a 32 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20 With readelf -Wl we also get the expected output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10 TEST=This fixes the 64 bit build on Cezanne with some follow-up patches applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-23Revert "mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE"Nick Vaccaro
This reverts commit 7203aa5c2dcb90e50356305cabbe062bd4f4dc76. BUG=b:260138434 TEST=None Cq-Depend: chrome-internal:5126951, chromium:4049177 Change-Id: Ieaa44a33a7c65d384581b5145821b449783ca3fa Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-23soc/mediatek: Add error handling for dptx_get_edid()Liju-Clr Chen
Skip eDP initialization when we failed to get EDID. This prevents the PLL assertion in dp_intf_config() if the display could not be initialized properly. BUG=b:233720142 TEST=boot to depthcharge on MT8188 EVB. Change-Id: I0fd672b175feb9b813c1d9ec4140e4273079ff07 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69858 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23src/soc/qualcomm: Remove unnecessary space after castsElyes Haouas
Change-Id: Ic6c711fe3fad19c24ca4c01f8d0a4bc002f14bd6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69807 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23sb/intel/i82801gx/lpc.c: Use post_code()Elyes Haouas
Use post_code() instead of 'outb(value, CONFIG_POST_IO_PORT)'. Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69901 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-23mb/google/skyrim/var/winterhold: Add Vrm setting for SMTEricKY Cheng
All parameters of DPTC_INPUT() need to be configured on devicetree when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without configurations on devicetree would be 0 when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document #57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA and vrm_soc_current_limit_mA on devicetree with thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoidany thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A. BUG=b:258572474, b:248976976, b:259167917, b:257394883 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-23soc/intel/meteorlake: Select X86_INIT_NEED_1_SIPI KconfigSubrata Banik
This patch helps to save 10.200ms of booting time without any issue seen during MP Init. All cores are out from reset and alive. Port the Alder Lake 'commit 6526e7896727 ("soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL")' also to Meteor Lake. Additionally, no performance degradation is observed while running benchmarks. BUG=b:211770003 TEST=Able to boot Google, Rex to ChromeOS with all cores enabled. Without this patch: 30:device enumeration 1,480,217 (28,232) With this patch: 30:device enumeration 1,472,466 (18,334) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iec21470b9b34514169789c39bdc3be4e4ff6c7b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69851 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23soc/intel/common: Define post codesMartin Roth
For the most part, this just moves the existing post codes into macros so that they're not just bare numbers. cache_as_ram.S: Post code 0x28 was previously pointless with just a single jump between it and post code 0x29, car_init_done. This code was removed, and the 0x28 value was used to differentiate the car_nem_enhanced subroutine from the other 0x26 post codes used before calling the clear_car subroutine. All other post codes remain identical. POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas the POST_SOC codes are expected to be Intel only. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23util/release/build-release: Fix style issuesMartin Roth
No real functional changes, just cleaning up shellcheck issues, putting braces around variables, add comments and the like. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6e79afc8d725e86ddbf7f4eb4685bed190c20738 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67319 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23cpu/intel/car: Define post codesMartin Roth
This moves a lot of post code values, but unifies them between platforms, so that the same value means the same thing as much as possible. The P4-netburst code was the most extensive and most different, so that dictated the majority of the values. Three were two values there that didn't match the other files, so those two values, 0x22 & 0x29 have duplicate entries in the table. The rest of the entries are similar between platforms, though the values for many of them were moved to match the P4-netburst values. POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become global, while POST_SOC would be specific to the Intel platforms. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69866 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22crossgcc: Remove leftover "../cmake"Elyes Haouas
"../cmake" introduced on Change-Id: I3144a83 Remove "../cmake" when the build is done. Change-Id: I289bfaca1fd8d3f004455babd99849ca8aa2d6db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-22mb/google/skyrim: Pass Ti50 IRQ to PSPMark Hasemeyer
It shouldn't be assumed that all variants of skyrim will use the same gpio for TPM interrupts. Use the PSP's new mailbox command to tell it what gpio the tpm interrupt comes in on. BUG=b:248193764 TEST=tast run <ip> hwsec.TPMContest Verify log entry:[DEBUG] PSP: Setting TPM GPIO to 18...OK Use incorrect GPIO in mailbox cmd and verify TPMContest test failed. Signed-off-by: Mark Hasemeyer <markhas@google.com> Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69874 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22util/crossgcc: Limit LLVM targets to the needed onesFelix Singer
coreboot only supports a small subset of the targets that LLVM supports. It's not needed to enable all possible targets. Thus limit the targets to the following ones: * X86 * RISC-V * AArch32 * AArch64 * PowerPC Change-Id: I9938bf176b5fe2b0a631c3b1ae858f988898a196 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69841 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur.heymans@9elements.com>
2022-11-22src/acpi: Remove unnecessary space after castsElyes Haouas
Change-Id: I3c077dee1c14e4aa45f837361daf799f02d32a29 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69818 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/commonlib: Remove unnecessary space after castsElyes Haouas
Change-Id: Ib20f02cc9e5be0efea8bc29fce6bd148adf28ead Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69817 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/arch: Remove unnecessary space after castsElyes Haouas
Change-Id: I00551dfd963d47a58284bc31f21b0fa12130fe78 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69816 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/northbridge: Remove unnecessary space after castsElyes Haouas
Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/soc/samsung: Remove unnecessary space after castsElyes Haouas
Change-Id: I32b41eded11e4e575627fec3947a75c08fdfd0a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69812 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/soc/cavium: Remove unnecessary space after castsElyes Haouas
Change-Id: Ieb094096e9e204e59a1f3fcf716d906e7736fb43 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69811 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/soc/nvidia: Remove unnecessary space after castsElyes Haouas
Change-Id: I096e88158027ac22cf93a9450c869807dbc14670 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69810 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/soc/mediatek: Remove unnecessary space after castsElyes Haouas
Change-Id: I871579cc434820294f285298fe43da4cd1da27a3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69809 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/soc/ti: Remove unnecessary space after castsElyes Haouas
Change-Id: If4564abf060410726b0b245ba002a35ca9d30769 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69808 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/southbridge: Remove unnecessary space after castsElyes Haouas
Change-Id: Ib82968724696110a8d1655928db5b2a665525d20 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69805 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/device/pci_: Remove unnecessary space after castsElyes Haouas
Change-Id: I11593245fedc26489e3506d773aaff1ad34188b1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69804 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/drivers: Remove unnecessary space after castsElyes Haouas
Change-Id: I16689da893b5a0c3254364759d435281cb3e1caf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69803 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/include: Remove unnecessary space after castsElyes Haouas
Change-Id: Ie6def0dab9ac37c0938b73d27148a49531c6b17f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69802 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/cpu: Remove unnecessary space after castsElyes Haouas
Change-Id: I12463d4d26c03c85fa018b421bb9166fbfeb0b60 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69801 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22security: Remove unnecessary space after castsElyes Haouas
Change-Id: Ibd41382d0e0ef58498ac925dc9e10b54a76a798a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69800 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22mb/google/nissa/var/nivviks,yaviks: Remove ISH firmware-nameReka Norman
For nissa, the ISH main firmware will be included in the CSE region in flash instead of loading it from rootfs. So remove the ISH firmware-name. BUG=b:234776154 TEST=Boot to OS on nirwen and yaviks UFS SKUs. Check ISH firmware is not loaded by kernel, and device still goes to S0i3. Cq-Depend: chrome-internal:5102230 Change-Id: I68f963e17bc0dbf9db9adaaa3f96f06b8737523b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69868 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-11-22mb/google/nissa/var/craask: Disable SAR Proximity Sensor GPIO pinTyler Wang
BUG=b:253387689 Test:Boot to OS on craask and check SAR Proximity Sensor GPIO pin Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I2b2a2516890b68036e96d1a542e6a10a098cb6a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69790 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-22drivers/ocp/dmi: move smbios_ec_revision to ocp folderJonathan Zhang
Move smbios_ec_revision to ocp folder so that all ocp boards share the same function without implementing again. TESTED=Execute "dmidecode -t 0" to check corresponding field. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Jonzhang Zhang <jonzhang@meta.com> Change-Id: I898662b78d3dbab1861cee6f1b6e148297a5d11b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22include/spd.h: Fix comment module type informationElyes Haouas
Change-Id: I7af61404d11f7e0ff5f30c42958c4dd9318538fa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-22util: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7cf35132df0bc23f7b6f78014ddd72d58ea2ab8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-22ec: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie5355e05982b372ef69515cfa081e2afbc7b09fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/68981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-21libpayload: Fix compiler warningsThomas Heijligen
Following warnings occur when compiling with `i386-elf-gcc (coreboot toolchain v2022-09-18_c8870b1334) 11.2.0` drivers/serial/8250.c:75: [-Werror=unused-variable] Move variable declaration inside the `#if !CONFIG(LP_PL011_SERIAL_CONSOLE)` block drivers/udc/dwc2.c:505: [-Werror=format=] use `%zd` to match type `size_t` Change-Id: Id285c24cba790f181fa203f3117e5df35bed27c4 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69764 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Allow jenkins builders to skip testing areasMartin Roth
With the addition of the clang tests, the jenkins builds are taking a really long time to run the tests. This change allows the "what-jenkins-does" build to be split into separate builds on jenkins. Additionally, some jenkins builds like coverity don't need (or want) to build clang or even the linters. Update help with the variables. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0f8ac68c1bc8f8ff9be62d80db850355e742ee74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Add scanbuild test build to what-jenkins-doesMartin Roth
This tests building a single target with scanbuild so to make sure that option hasn't been broken. Since it's a different type of build, it hasn't previously been tested with what-jenkins-does. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8a74dac203f4d38c0cb30a0b64724e6f9095b9dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/69861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Use new --name argument for abuildMartin Roth
This gets rid of the duplicated directory and xml filename and uses the --name argument to abuild instead, which also updates the test name in the junit xml file. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ibe538da42280696190b0a7a0c63fd86a63e40214 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/abuild: Add --name option to set name of abuild runMartin Roth
Previously, the testclass variable was only updated with the chromeos or Kconfig option values, and the output directory and xml file names were updated independently. With the --name option, all of these can be set simultaneously. This also prevents jenkins from seeing clang and gcc tests as the same because the testclass variable wasn't updated. If --name is not set, all behavior is as it was previously. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8f52779b92d213386a3eb371d1f30ee32ed48b85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69859 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Call test-tools target from what-jenkins-doesMartin Roth
Instead of having duplicate lines in the what-jenkins-does target and the test-tools target, make test-tools from what-jenkins-does. Now there's only one place to update when changing the call. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id62d6bb1e729892ec123ea970ca8a31e03a812d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Update ABUILD_OPTIONS with long option namesMartin Roth
It's hard to tell what is what with the short option names, so use the long options here. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1371e098bba1077dedfaffa56287a28656197b40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69837 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Call test-abuild target from what-jenkins-doesMartin Roth
Instead of having duplicate lines in the what-jenkins-does target and the test-abuild target, make test-abuild from what-jenkins-does. The test-abuild target had not been updated to use the ABUILD_OPTIONS variable, so update it with the commands from what-jenkins-does. Now there's only one place to update when changing the call. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4552193894c16301defb851eb3db4bdfbfa49803 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Call test-lint target from what-jenkins-doesMartin Roth
Instead of having duplicate lines in the what-jenkins-does target and the test-lint target, make test-lint with the --junit argument from what-jenkins-does. Now there's only one place to update when changing the call. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2f90df76126f453fbcd91f4c4af5d784ac2dbe88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Unify cleanup in all targetsMartin Roth
Instead of having the what-jenkins-does target clean up before building, have it call the test_cleanup target. Clean the tegra targets. Remove distclean from test_cleanup target - I don't think that's expected, and people might be upset by having their .config deleted. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia9d585df05343365c89e49b1c01dba9ba865003f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>