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authorFelix Held <felix-coreboot@felixheld.de>2022-11-22 20:02:46 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-11-23 19:43:46 +0000
commit3b89c959061f878d96b7ae7b88c3a1386489a1b8 (patch)
treeb49d9a30844837b470e3ec0916aefaba08b1f2c7
parent170bc7a0feb5c148b34a49eeae4e6745e242a228 (diff)
soc/amd/*/Makefile: fix readelf parameters to get bootblock size
This ports forward part of commit df0968062622 ("soc/amd/picasso: Add support for 64bit builds") to the newer AMD SoCs. Use -Wl instead of -l to get the output format that the commands in the Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this change, readelf will split the output into two lines in case of a 64 bit coreboot build. This results in invalid amdcompress and amdfwtool command lines which will cause the amdfwtool call to fail with Error: BIOS binary destination and uncompressed size are required With the old readelf -l command we get this output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000 0x0000000000010000 0x0000000000010000 RWE 0x10 while we get the correct output in a 32 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20 With readelf -Wl we also get the expected output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10 TEST=This fixes the 64 bit build on Cezanne with some follow-up patches applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
-rw-r--r--src/soc/amd/cezanne/Makefile.inc4
-rw-r--r--src/soc/amd/glinda/Makefile.inc4
-rw-r--r--src/soc/amd/mendocino/Makefile.inc4
-rw-r--r--src/soc/amd/morgana/Makefile.inc4
4 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 1f2bb6d6e8..091e63f411 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -141,8 +141,8 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
# type = 0x62
PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
PSP_ELF_FILE=$(objcbfs)/bootblock.elf
-PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
-PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
+PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
+PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
# type = 0x63 - construct APOB NV base/size from flash map
# The flashmap section used for this is expected to be named RW_MRC_CACHE
diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc
index e00421d52c..4d1ba5584d 100644
--- a/src/soc/amd/glinda/Makefile.inc
+++ b/src/soc/amd/glinda/Makefile.inc
@@ -141,8 +141,8 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
# type = 0x62
PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
PSP_ELF_FILE=$(objcbfs)/bootblock.elf
-PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
-PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
+PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
+PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
# type = 0x63 - construct APOB NV base/size from flash map
# The flashmap section used for this is expected to be named RW_MRC_CACHE
diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc
index 92c75f8ded..ab709e6ce6 100644
--- a/src/soc/amd/mendocino/Makefile.inc
+++ b/src/soc/amd/mendocino/Makefile.inc
@@ -142,8 +142,8 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
# type = 0x62
PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
PSP_ELF_FILE=$(objcbfs)/bootblock.elf
-PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
-PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
+PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
+PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
# type = 0x63 - construct APOB NV base/size from flash map
# The flashmap section used for this is expected to be named RW_MRC_CACHE
diff --git a/src/soc/amd/morgana/Makefile.inc b/src/soc/amd/morgana/Makefile.inc
index a88e1a5437..44a92eb5b7 100644
--- a/src/soc/amd/morgana/Makefile.inc
+++ b/src/soc/amd/morgana/Makefile.inc
@@ -141,8 +141,8 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
# type = 0x62
PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
PSP_ELF_FILE=$(objcbfs)/bootblock.elf
-PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
-PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
+PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
+PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
# type = 0x63 - construct APOB NV base/size from flash map
# The flashmap section used for this is expected to be named RW_MRC_CACHE