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Updating from commit id 4b12d392e5b1:
scripts: Add a script to convert a vbprivk to a PEM
to commit id f1f70f46dc54:
2lib: Add gbb flag to enforce CSE sync
-Subproject commit 4b12d392e5b12de29c582df4e717b1228e9f1594
+Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2
Change-Id: I2c5b603ce5ea49e6c1aec293960184d84eedd1e7
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The ROTM method should return a package:
```
Name (RBUF, Package (0x03)
{
"0 1 0",
"1 0 0",
"0 0 1"
})
Return (RBUF)
```
Adjust the acpigen to do this.
Change-Id: Id493f6955c1d0dc3449402262a8575091a828226
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Clang builds (bootblock: 20800 bytes) are slightly larger than GCC
builds (bootblock: 18688 bytes) so increase the size of both bootblock
and romstage.
The technical reference manual mentions no upper limit to the size of
the bootblock in the TI header so increasing the bootblock size is
allowed.
To be able to link the clang bootblock increase it from 20K to 22K.
Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.
BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.
Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83746
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The previous uploaded verb table is not fully applied due to
configuration error. Uploaded the verb table provided by Realtek which
can be found in b:336967284.
BUG=b:326412504, b:336967284
TEST=deploy and check volume
Change-Id: Ib9a8248c4a437fd204f40918d801a4a010a5c4df
Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Terry Cheong <htcheong@chromium.org>
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DC offset of class-D amplifier is 7mV in Brox which is larger than the expected 3mV.
Add a section in the verb table to enable class-D calibration based
on the updated verb table provided by Realtek in b:342506575 comment#6.
This improves the offset to be less than 1mV.
BUG=b:342506575
BRANCH=main
TEST=Verify DC offset of speaker amplier output is less than 1mV with a multimeter when \
playing -100dB sine waves.
Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create the jubilant variant of the brox reference board by copying
the template files to a new directory named for the variant.
BUG=b:348543712
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_JUBILANT.
Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83212
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
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The PSP can send SMIs to the x86 side of the system. Add helper
functions to configure and to reset the PSP SMI generation. Since
Stoneyridge also selects SOC_AMD_COMMON_BLOCK_SMI, add the SMITRIG0_PSP
define and rename SMITYPE_FCH_FAKE0 to SMITYPE_PSP in its SoC-specific
smi.h to bring it in line with the newer SoCs.
This patch is split out from CB:65523.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83702
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to detect more issues in our code, make GCC more picky by
enabling -Wextra. Disable a couple of warnings turned on by -Wextra
temporarily in order to keep everything compiling and working for now.
The warnings may be enabled step by step later.
Since xcompiles applies to coreboot and libpayload, add Wextra here
instead of the top-level Makefile.mk.
Change-Id: I60915cb66581dc2c9b6807335fd0e214b45e76d6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83347
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The Windows drivers require the subsystem ID to match on the PCI
device, so set these to allow the driver to install.
Change-Id: I01b36554d5322018efc72734a8e749cc06263577
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83621
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SMRAMC, C_BASE_SEG, G_SMRAME, D_LCK, D_CLS, D_OPEN, ESMRAMC, T_EN,
TSEG_SZ_MASK and H_SMRAME are already defined in included "q35.h" file.
Change-Id: Ic3c01cca14749f77adecc327a78ac011ba3f4c0b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83429
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"0x1502 F81804 chipset ID, same for F81966" in
https://web.archive.org/web/20240628153609/https://github.com/torvalds/
linux/blob/master/drivers/gpio/gpio-f7188x.c
Change-Id: I6889ad8ad861465316333ff997956a05b74c5855
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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acpigen_write_pci_root_port writes SSDT device objects for PCIe
root port, _ADR and _BBN are provided. SSDT objects for direct
subordinate devices will also be created (if detected), _ADR and
_SUN are provided.
TEST=Build and boot on intel/archercity CRB
Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0
Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Create the teliks variant of the nissa reference board by copying
the anraggar files to a new directory named for the variant.
BUG=b:352263941
BRANCH=None
TEST=1. util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TELIKS
2. Run part_id_gen tool without any errors
Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768
Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83408
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch supports keyboards that have delete key but without
numpad.
To prevent KEY_DELETE be defined twice, move it from
numeric_keypad_keymaps to rest_of_keymaps.
BUG=b:345231373
TEST=Build and test on Riven/Craaskino, delete key function
works
Change-Id: Ib922a2b52fa7152ba3d9deb44e2c8200b2a3802c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83684
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.
BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.
Change-Id: I4a24fb69ebec87f65b679cde0e4a1a8827cd365d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83722
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Since the P2C_BUFFER_MAXSIZE value will be needed in another compilation
unit, move the define to the common psp_def.h. P2C_BUFFER_MAXSIZE is
moved there too for consistency reasons.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d4d93760c90ad6e0ecadf70600b1d697a02fa82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83701
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When sending mailbox commands to the PSP from SMM, the SMM flag needs to
be set right before sending the mailbox command and cleared right after
the command is sent. In order to not have this code duplicated, factor
it out into a function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3628463dece9d11703d5a068fe7c604108b69c1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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The reasoning behind this and the positive side effects of this aren't
too clear from the code, so point those out in a comment.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4f4121031fc1ef600cdf5551f61f1ef4e03b56a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Since it's not exactly obvious what 'c2p_buffer', 'p2c_buffer' and
'smm_flag' are used for, add comments to those.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ec092a92fe9f0686ffb7103e441802fc05381f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Rename the 'domain' element of the 'domain_path' struct to 'domain_id'
to clarify that this element is the domain ID.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83677
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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To avoid having constructs like 'dev->path.domain.domain' in the SoC
code, create the 'dev_get_domain_id' helper function that returns the
domain ID of either that device if it's a domain device or the
corresponding domain device's domain ID, and use it in the code.
If this function is called with a device other than PCI or domain type,
it won't have a domain number. In order to not need to call 'die',
'dev_get_domain_id' will print an error and return 0 which is a valid
domain number. In that case, the calling code should be fixed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83644
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In accordance with the F81962/F81964/F81966/F81967 datasheet:
Release Date: Feb, 2018, Version: V0.18P [1].
[1] https://web.archive.org/web/20240707052102/http://
www.jetwaycomputer.com/download/Fintek/F81966_wdt_gpio.zip
Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In accordance with the F81866A datasheet:
Release Date: Jan, 2012, Version: V0.14P [1].
[1] https://web.archive.org/web/20240707051837/http://www.
jetwaycomputer.com/download/Fintek/F81866_wdt_gpio.zip
Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83004
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some chips (fintek [1,2]) have registers with specific selector-fields
that can affect the address space of the device (for example, switch the
register bank). At the same time, these registers contain fields that
should not change after they are configured in BIOS (for example, set
the port to 2E/2F or 4E/4F). In this case, the selector should take into
account the mask of the register fields and there is no convenient and
easy way to add this in the code in the utility. The selector-fields
should be set manually before the dump and this action is done several
times.
This patch adds an extra-selector mechanism that allows superiotool to
make a correct dump in automatic mode.
Just add a structure with an index, mask, and value for the selector
inside the superio_registers chip for the corresponding LDN to switch
the register bank:
{FINTEK_F81966_DID, "F81962/F81964/F81966/F81967", {
* * *
{NOLDN, "Global",
{0x28,0x2a,0x2b,0x2c,EOT},
{0x00,0x00,0x00,0x00,EOT},
{.idx = 0x27, .mask = 0xd, .val = 0x1} /* update extra selector */
},
{0x03, "LPT",
{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
{NANA,0x03,0x78,0x07,0x03,0xc2,EOT} /* without extra selector */
},
* * *
Tested with Fintek F81966 on Asrock IMB-1222:
- run superiotool on Ubuntu and dump the registers for the board with
the vendor's firmware;
- add the superio chip initialization code to the board configuration
in coreboot and build the project;
- boot Ubuntu on the board with coreboot and re-dump the registers;
- the register values from the board configuration code are the same
in both dumps.
Found Fintek F81962/F81964/F81966/F81967 (vid=0x3419, id=0x0215) at 0x2e
(Global) -- ESEL[27h] 0x00 (Port Select Register) --
idx 02 07 20 21 23 24 25 26 27 28 29 2a 2b 2c 2d
val 00 0b 15 02 19 34 5a 23 80 a0 f0 45 02 e3 2e
def NA 00 15 02 19 34 00 23 02 a0 00 00 02 0c 28
* * *
The changes do not affect the configuration of existing chips, which
was tested on the Asrock H110-STX motherboard with Nuvoton NCT5539D
(the dump before and after the changes are the same).
[1] CB:83004
[2] CB:83019
Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83196
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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During the stages which use Cache-as-RAM (CAR), coreboot needs more than
1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs
for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is
estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly.
BUG=None
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch drops fw_config probing for ISH because ISH IP should
remains on by default for all Trulo variants.
Additionally, removed the redundant ISH entries from variant
override devicetree.
BUG=b:354607924
TEST=Able to verify ISH PCI Device is available while booting eMMC sku.
```
lspci
00:00.0 Host bridge: Intel Corporation Device 461c
...
00:12.0 Serial controller: Intel Corporation Device 54fc
...
00:1a.0 SD Host controller: Intel Corporation Device 54c4
```
Also, able to enter S0ix with this patch.
```
> suspend_stress_test -c 1 --ignore_s0ix_substates
At AP console:
s0ix errors: 0
s0ix substate errors: 0
s0ix pc10 errors: 0
At EC console:
power state 5 = S0ix, in 0x38d87
```
Change-Id: Ic1e415ec848ac91a9bbf21b26597f4e6b5f7a1f5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83695
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reduce PchPmSlpAMinAssert (pch_slp_a_min_assertion_width) to minimum
time (98ms) from 2sec.
BUG=b:349595391
BRANCH=firmware-brya-14505.B
Test=Verified on xol
Change-Id: Ia4b7b7ab5dc9afeb3505dfd2b42d0d397aed7a5c
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83683
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Streamline variant-level overrides by removing redundant entries that
already exist in either the SoC-level or the platform-level configurations.
BUG=None
TEST=emerge-nissa coreboot
Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: Idcdd3e2525b621310aaf43608fd5fede8133d16a
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83675
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Chip Direct Mapping is exclusive to Windows; it allows specifying the
position where a chip is mounted. There are 8 positions and a _CDM
method should return 0xabcd0X, where X is the position.
Tested by booting Windows 11 on the StarLite Mk V, rotating the device
and checking the orientation is correct, where previously, it was
inverted.
Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81409
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The comment for the BOOTBLOCK region should be written right above the
BOOTBLOCK declaration.
BUG=b:317009620
TEST=none
BRANCH=none
Change-Id: I7afdf74844a9d97169b4e4a23c3c9c6060e886d9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 59ee65d271c7c617bcc240019231da4f0bd04db6.
Reason for revert:
- Usb4CmMode & CnviWifiCore Upds are available starting with TWL FSP
version v5222.01. Therefore, no special handling is required.
BUG=b:330654700
TEST=Able to build google/tivviks.
Change-Id: I3c74ec5b9924e88a26984fe8d3275ba80edb14ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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This change adds a new USB2 Bluetooth device configuration on Port 10
for the Trulo variant.
* A new `drivers/usb/acpi` chip is added with:
* `desc` set to "USB2 Bluetooth"
* `type` set to "UPC_TYPE_INTERNAL"
* `reset_gpio` set to "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
* `device` referencing `usb2_port10`
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I9a92a4d008eb4d0c339079ecbbb77facece435ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This change removes the configuration for the unused USB2 Port 6
(index 5) and its associated Bluetooth device on the Trulo variant.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I9970274b9b1b1076a2f9d649d61c825cac71d0c7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83665
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rishika Raj <rishikaraj@google.com>
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This change removes the configuration for the unused USB2 Port 6
(index 5) and its associated Bluetooth device on the Orisa variant.
It also cleans up a redundant newline before the `serial_io_i2c_mode`
definition.
BUG=b:351976770
TEST=Builds successfully for google/orisa.
Change-Id: Icf1ff442530ad2263ad0b58829e5c7b2ce544439
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83664
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rishika Raj <rishikaraj@google.com>
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This patch moves the configuration for integrated Bluetooth
functionality (USB2 Port 9) from Orisa variant to the Trulo baseboard.
This change is necessary to support the CNVi BT module on Trulo
variants. The configuration is skipped for Orisa.
Trulo: USB2 Port 9 is now configured as USB2_PORT_MID(OC_SKIP) to
support the CNVi BT module.
Orisa: The previous configuration of USB2 Port 9 as a Bluetooth port for
CNVi WLAN has been removed.
This change ensures proper Bluetooth connectivity is applicable for all
Trulo variants including Orisa and Trulo.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83663
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add STORAGE_UNKNOWN fw_config to enable all storage devices.
2. Update fw_config probe to enable/disable devices in devicetree.
3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config
is enabled.
BUG=None
TEST=emerge-nissa coreboot
Change-Id: Id3a22aa2206e86fdca6f6fadbc849572890fee58
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83657
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Orisa variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
BUG=b:345112878
TEST=Able to enter S0ix on Orisa eMMC sku after disabling UFS
during boot path.
Change-Id: I969b0c0c785ed4c408f6fc6de71e7d0c1a1ea27c
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Also take the chance to sort the headers.
BUG=none
TEST=none
BRANCH=none
Change-Id: I9d487a40d0c58c6458b8b7d32b6401093fa417e7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83651
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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- Add Usb4CmMode & CnviWifiCore Upd support in FspsUpd.h
- Update UPD Offset in FspsUpd.h
BUG=b:354612775
TEST=Able to build and boot google/Tivviks
Change-Id: Ia68b6aa90c782a359b594f381e223772a897c6e6
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Trulo variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
Note: Enabling this config would introduce an additional warm reset
during the cold-reset scenarios due to the function disabling of the
UFS controller as results we are expecting ~300ms higher boot time
(which might not be user visible because `cbmem -t` can't include
impacted boot time due to in-between resets).
BUG=b:355384185
TEST=Able to enter S0ix on Trulo eMMC sku after disabling UFS
during boot path.
Able to grep below debug prints while booting the eMMC sku.
[INFO ] FW_CONFIG value from CBI is 0x20000000
[INFO ] Disabling UFS controllers
...
[INFO ] fw_config match found: STORAGE=STORAGE_EMMC
Change-Id: I06a84fa8c3843edae5932e19d394b18b72ace422
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83654
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
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TEST=Able to build google/rex.
Change-Id: I0de87a2ff5ecb37f00ec745ad930e83f6356a3fe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83637
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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System76 EC since system76/ec@80cfa91b9fd5 ("acpi: Report RPM values
instead of raw tachometer values") performs the RPM calculation itself
and stores it in EC RAM where previously the raw tachometer values were
saved. The SBIOS is no longer required to make the conversion.
Change-Id: I82a4e25a8ce0f274b2d98e7ff2b12595acf6c3c5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Not setting tcss_aux_ori in devicetree is the same as
setting it to zero so remove it.
Change-Id: Ia0e90179dd05b23f1f36935be51327250c5a8684
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Currently we include a header file from the opensbi submodule.
That causes some issues, since we merge outside code with our own.
Most recently there have been made attempts to make the coreboot
codebase C23 ready. The code that we include from opensbi however causes
the build to fail, since it is not C23 ready.
This patch effectivily detaches the coreboot codebase from the opensbi
codebase and just copies the structure and definitions that we need from
opensbi into coreboot.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9d8f85ee805bbbf2627ef419685440b37c15f906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83641
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a helper function to read the reg property from an unflattened
device tree.
It also factors out the common code into a new function called
`read_reg_prop`.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7846eb8af390d709b0757262025cb819e9988699
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Update wake-up type, mainboard feature flags and enclosure type.
All other info are used from src/lib/smbios_defaults.c
Change-Id: I8a7d4958171df121e2cd3acb3a71554c695d64ab
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Update wake-up type, mainboard feature flags and enclosure type.
All other info are used from src/lib/smbios_defaults.c
Change-Id: I8e68c057fefa1d408fb8d69fef066cb573c929a4
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83328
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add sample DIMM slot configuration table for avenuecity CRB
and beechnutcity CRB. This table will be used to fill SMBIOS
type 17 table.
TEST=Boot on intel/avenuecity CRB
It will help to update Locator, Bank Locator and Asset Tag
with the value described in dimm_slot_config_table
Change-Id: I53556c02eb75204994a1bcb42eccb940e83bd532
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to
512KB + 32KB, addressing a requirement specified by coreboot where
stack usage is higher than 1KB alone.
BUG=None
TEST=None
Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83540
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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In order to clean up a bit, drop devices which are equivalent to the
ones from chipset devicetree.
Change-Id: I92765b404508901c7e84fad0bca30489cf69abac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83456
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The chromeec submodule is the largest submodule being pulled into the
coreboot tree, at over 400MB. The main branch also contains the majority
of these commits, so restricting it to a single branch still fetches
over 350MB.
Because there is only a single mainboard directory that enables the
build of the chromeec codebase by default, most people are fetching this
repo for no reason.
Based on this, we're going to change the way that the chromeec submodule
is used, fetching it the way we currently fetch external payloads. This
gives us 2 large advantages:
1) Only builds that actually need the chromeec repo will pull it down.
2) Each board that wants to build the chromeec codebase can use a
different commit, unlike submodules which all use the same "current"
commit.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I357c4c9b506dd3817a308232446144ae889bc220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Since the EC and PD firmware sources are now limited to two options -
'none' and 'external' - drop the choice selection and make the
EC and PD external options independent.
TEST=build google/lulu with external EC binary using existing defconfig
Change-Id: Ie37ff3a188b414fd099fbb344858bca4df419086
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83639
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In preparation for dropping the Chrome-EC submodule, remove the ability
for Chrome-EC and PD components to be built as part of coreboot.
These components have not been used or buildable for many years.
Change-Id: Ibf6bd43e755cf5b4d2aa8a42f38dc52e7023e9b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83638
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Now that we have a get_psp_mmio_base function that will work on all SoCs
that use the psp_gen2 code, we can move back to accessing the PSP
registers via their MMIO mapping. This sort-of reverts
commit 198cc26e4951 ("soc/amd/common/block/psp/psp_gen2: use SMN access
to PSP").
When doing SMN accesses from the SMI handler after the OS has taken over
ownership of the platform, there's the possibility to cause trouble by
clobbering the SMN access index register from SMM. So that should be
either avoided completely or the SMI code needs to save and restore the
original contents of the SMN index register.
The PSP MMIO base will be set up by the FSP before the resource
allocation in coreboot and be treated like a fixed resource by the
allocator. The first SMI where corresponding handler calls
'get_psp_mmio_base' happens when ramstage triggers the APM_CNT_SMMINFO
SMI right after mpinit which happens after the resource allocation. So
the PSP MMIO base address is expected to be configured and so the
'get_psp_mmio_base' function will cache the base address and won't need
to do any SMN access in subsequent calls that might happen after the OS
has take over control.
This isn't currently an issue, since the only PSP mailbox command from
the SMI handler after coreboot is done and the OS has taken over will
be during the S3/S4/S5 entry, and this will be triggered by the OS as
the last step after it is done with all its preparations for suspend/
shutdown. There will however be future patches that add SMI-handlers
which can send PSP mailbox commands during OS runtime, and so we have
to make sure we don't clobber the SMN index register.
TEST=PSP mailbox commands are still sent correctly on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I25f16d575991021d65b7b578956d9f90bfd15f6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83448
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This sort-of reverts commit 00ec1b9fc7ba ("soc/amd/common/block/psp/
psp_gen2: simplify soc_read_c2p38") and is done as a preparation to
switch back to using the MMIO access to the PSP mailbox registers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icca3c7832295ae9932778f6a64c493e474dad507
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Add get_psp_mmio_base which reads the PSP MMIO base address from the
hardware registers. Since this function will not only be called in
ramstage, but also in SMM, we can't just look for the specific domain
resource consumer like it is done for the IOAPICs in the northbridge,
but have to get this base address from the registers. In order to limit
the performance impact of this, the base address gets cached in a static
variable if an enabled PSP MMIO base register is found. We expect that
this register is locked when it was configured and enabled; if we run
into the unexpected case that the PSP MMIO register is enabled, but not
locked, set the lock bit of the corresponding base address register to
be sure that it won't change until the next reset and that the hardware
value can't be different than the cached value.
This is a preparation to move back to using MMIO access to the PSP
registers and will also enable cases that require the use of the MMIO
mapping of the PSP registers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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The PSP code introduced in a following patch needs both SoC-specific
functions get_iohc_info and get_iohc_non_pci_mmio_regs to also be
available in SMM, so add those compilation units to the corresponding
target.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e32084b45f07131c80b642bc73d865fc57688a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Instead of implementing the functions get_iohc_misc_smn_base and
get_iohc_fabric_id in the SoC code, move those functions to the common
AMD code, and implement get_iohc_info in the SoC code that returns a
pointer to and the size of a SoC-specific array of domain_iohc_info
structs that contains the info needed by the common code instead. This
allows to iterate over the domain_iohc_info structs which will be used
in a later patch to find the PSP MMIO base address in both ramstage and
smm.
TEST=Mandolin still boots and all non-PCI MIO resources are still
reported to the resource allocator
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifce3d2b540d14ba3cba36f7cbf248fb7c63483fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83443
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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No need to open-code this when we have a function for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iae570ba750cb29456436349b4263808e2e410e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83643
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Move is_domain0 and is_dev_on_domain0 from the Intel Xeon SP code to the
common coreboot code so that it can be used elsewhere in coreboot too,
and while moving also implement it as functions instead of macros which
is more in line with the rest of helper functions in that new file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I954251ebc82802c77bf897dfa2db54aa10bc5ac4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83642
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MAINBOARD_VENDOR is already provided by the Kconfig file on the vendor
level, so there's no need to redefine it to the same value at the
mainboard level.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icfcbcec005fadb8eaf1b8f90e1d71b3c6ee32088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83640
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank
selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver
accesses VBNV via Bank 0, the bit must be cleared before we can save
VBNV to CMOS in verstage.
Usually there's no problem with that, because the Register A is
configured in cmos_init() in ramstage. However, if CMOS has lost power,
then in the first boot after that, the bit may contain arbitrary data in
verstage. If that bit happens to be 1, then CMOS writes in verstage will
fail.
To fix the problem, define vbnv_platform_init_cmos() to call
cmos_init(0), which will configure the Register A and therefore allow
saving VBNV to CMOS in verstage.
[1] 48751_16h_bkdg.pdf
BUG=b:346716300
TEST=CMOS writes succeeded in verstage after battery cutoff
BRANCH=skyrim
Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83495
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Fn key on riven emits a scancode of 94 (0x5e).
BUG=b:345231373
TEST=Flash riven, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: Iddedd08fc50e8e8e369ce3d73edf0f3077867e87
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83614
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Multiply before dividing to improve accuracy of the result.
Change-Id: I974cad3af4e1f86ae58e90c68db463fc436223af
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83619
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures GPIO pins as required for booting the Trulo
device from ramstage.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I7b540416083a923ba4d2e52aa8edafb4bfb9ac0e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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When we tried to add CMOS support to PSP verstage (CB:83495), the clang
builds failed on boards with cezanne SoC (such as Guybrush), due to
over-sized verstage. On the other hand, there is no such problem for gcc
builds on the same boards.
Building PSP verstage by clang generates much larger verstage size (81K)
compared with using gcc (67K). To unblock adding features to verstage,
temporarily enable -Oz for clang builds.
Change-Id: I033458556986ade88fb8e68499b632deae4dd419
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: If514ee7c1174d13b8ca8eb7fd20359e0730a8893
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83525
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to clean up a bit, drop devices which are equivalent to the
ones from chipset devicetree.
Change-Id: Ie485684747efccb8fb0ab87f10694c52a98f3c88
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83455
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 48f1bc9f5:
2024-05-02 10:13:54 +0200 - (Merge "feat(zynqmp): remove unused pm_get_proc_by_node()" into integration)
to commit id c5b8de86c:
2024-07-22 18:07:11 +0200 - (Merge "feat(debugv8p9): add support for FEAT_Debugv8p9" into integration)
This brings in 447 new commits.
Change-Id: I0a24e2b2b83d18d5ce8f3b1af710b5acde996ad0
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Updating from commit id b6f44e62:
2024-07-01 04:30:14 +0000 - (futility: updater: Increase try count from 8 to 10)
to commit id 4b12d392:
2024-07-17 01:47:56 +0000 - (scripts: Add a script to convert a vbprivk to a PEM)
This brings in 9 new commits:
4b12d392 scripts: Add a script to convert a vbprivk to a PEM
033d7bfa futility: updater: Increase try count from 10 to 11
f63e088e treewide: Ensure a space after if/for/while keywords
17a45712 2auxfw_sync: Clear display request before EC reset
e529f947 2ec_sync: Reactivate VB2_CONTEXT_EC_SYNC_SLOW
ca2d42d1 Android: Explicitly disable v1/v2 signing when using apksigner
fc7a7a5d futility: flash: Print ro_start and ro_len for debug
86542905 Migrate to new Android.bp build system
aa35a020 host/lib/host_p11_stub: Add missing includes
Change-Id: Ida8a27dcb0acf83022aff0118827e3d310fae1a5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83612
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As of commit 3f0bb2fb0741 (autoport: Add support for Haswell-Lynx Point
platform), autoport supports Haswell in addition to Sandy Bridge and Ivy
Bridge.
Change-Id: Iccc10441389580ff8e89c3718484d25d20970f68
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialise overridetree based on the schematics revision 20240715.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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TEST=Build and boot on archercity CRB
No changes in boot log and 'dmidecode' result under centos
TEST=Build and boot on avenuecity CRB
It will add DMI type 16,17,19,20
Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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No assembly.inc file is being generated by romcc anymore.
The -I. was only used in a single place that can use the common -Isrc
instead.
Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83563
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no difference in how early and later stages are linked so
rename the same function.
Change-Id: I458c7c6822b310847e7ab32519fd8d66a90f88f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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We only use the bfd linker currently but partial linking is not
supported by other linkers and is also a problem for LTO.
Change-Id: I3b23d86e604229262d7c762e23bb963a0e944b5d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71910
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No need to have separate sections, and will be cleaner when adding
another section in a subsequent patch.
Change-Id: I4ad6be9dd67b5adbc9c5b0fcab51ce0c54351173
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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It is a new incoming Protectli product based on Alder Lake-P SoC.
More details and documentation will be added later.
TEST=Boot Ubuntu 22.04 LTS and Windows 11 on VP6670.
Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80501
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add mainboard folder and drivers for new reference board 'Rauru'.
TEST=saw the coreboot uart log to bootblock
BUG=b:317009620
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83573
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new folder and basic drivers for Mediatek SoC 'MT8196'.
Refer to MT8196_Chromebook_Application_Processor_Datasheet_V1.0 for
MT8196 SPEC detail.
This patch also enables UART and ARM arch timer.
TEST=saw the coreboot uart log to bootblock
BUG=b:317009620
Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Xol has a shutdown issue on our reliability test environment:
- High temperature
- No battery condition
It needs to have margin for the PL2 and PL4 values from the adapter
power, this will limit the PL2/PL4 values up to 30W/40W for xol's
45W power adapter. The new values are confirmed by our power team.
BUG=b:353395811
BRANCH=brya
TEST=built and verified MSR PL2/PL4 values.
Intel doc #614179 introduces how to check current PL values.
[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
constraint_0_power_limit_uw:18000000 <= MSR PL1 (18W)
constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)
[When connected 60W adapter without battery]
Before:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:60000000
After:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:30000000
constraint_2_power_limit_uw:40000000
[When connected 45W adapter without battery]
Before:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:45000000
constraint_2_power_limit_uw:45000000
After:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:30000000
constraint_2_power_limit_uw:40000000
Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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It looks like some unused artifact: The PPC64 Makefile.mk doesn't
pick it up. Also, the only other architecture using this (x86) has
linker flags there, not compiler flags.
Change-Id: I734542db9ee5b62d9a39d303d4092cd83dfef54b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A
is bank selection. Since the MC146818 driver accesses VBNV via Bank 0,
the value set in cmos_init() must not contain that bit.
To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add
an static assertion about the bank selection for AMD. Note that the
kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/rtc/rtc-mc146818-lib.c?id=3ae8fd4157
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: I6122201914c40604f86dcca6025b55c595ef609e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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One smbios type 4 should be provided for each CPU instance.
Create SMBIOS type 4 entry according to socket number, with a
default value of 1.
TEST=Boot on intel/archercity CRB
No changes in boot log and 'dmidecode' result under centos
Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83331
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If user continues to use the touchpad for over 3 minutes on Xol, the
pointer movement is stuttering.
Touchpad I2C transaction should appear during the interrupt signal level
is low, but we could see some more I2C transaction after the interrupt
signal(GPP_F14) went to high.
We found experimentally that changing the interrupt type to GPIO_INT
from APIC_IRQ improved this issue. We are still investigating, would
like to apply this change first for Xol's dogfooding.
BUG=b:350609957
BRANCH=brya
TEST=built and verified there's no stuttering issue on touchpad movement
Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
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This change adds early and romstage GPIO configurations for the trulo
variant, including:
Early GPIOs:
- GSC (Google Security Controller)
- WP (Write Protect)
- UART0 (for serial debug)
Romstage GPIOs:
- Touch Screen early power sequencing
CrOS GPIOs:
- CROS_GPIO_VIRTUAL
- GPIO_PCH_WP
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ic1b84f61ef62ddbadc2a45758fb3fce90fce0e88
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83568
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch adds FW Config to the device tree for choosing between the
discrete PD chip.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I0a8fb0225edecb063dede31efaec6f2502476977
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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This patch adds power related entries (FIVR and policy to control
lower power c-state transitioning) to the device tree.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ib125c91be79a81f3103dcd587dc685134a292e03
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This patch adds Thermal related entries (like, TDP, TCC and enabling
DPTF config with required sensor configuration) to the devicetree.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83565
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
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TEST=Build Pass.
BUG=b:317009620
Change-Id: Ida203a72c23b94b1848418c9727a5788df421eea
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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To reduce duplicate memmory macros of MediaTek SoCs,
move the header file to a common directory.
TEST=Build geralt pass
BUG=b:317009620
Change-Id: Iea4add8fe3735085c13438a2e177bec177913191
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83571
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To reduce duplicate region declarations of MediaTek SoCs,
move the header file to a common directory.
BUG=b:317009620
TEST=Build geralt pass.
Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83570
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Suppress the warning:
missing .note.GNU-stack section implies executable stack
NOTE: This behaviour is deprecated and will be removed in a
future version of the linker
Since we don't need an executable stack this is fine. Some newer
linkers like LLD even default to this.
Change-Id: Ib787cc464e0924ab57575cec9fbfd1d59bdd3481
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Silence a linker warnings about segments with RWX. Having one segment
for all sections is a good design choice as it makes parsing the elf
into a loadable binary simpler.
Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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create_ioat_domain creates the domain device with a number of
resources. Return the updated resource index so that the updated
index could be used as the starting index for additional resource
creation outside create_ioat_domain.
TEST=Build and boot on intel/archercity CRB
Change-Id: I9e719ae8407c7f31f88dbb407f003e2ded8f0faf
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch enables LZMA or LZ4 compression algorithm for the logo cbfs
file based on BMP_LOGO_COMPRESS_LZMA or BMP_LOGO_COMPRESS_LZ4 Kconfig.
Logo cbfs file is compressed based on CBFS_COMPRESS_FLAG, by default.
Based on logo file content and target platform, enabling LZ4 could
save significant boot time, with increase in file size.
For brox:
cb_logo LZ4 is +1265 bytes than LZMA, saves ~0.760ms in decomp.
cb_plus_logo LZ4 is +2011 bytes than LZMA, saves ~0.880ms in decomp.
BUG=b:337330958
TEST=Able to boot brox and verified firmware splash screen display
with LZMA and LZ4 compression.
Change-Id: I57fbd0d3a39eaba3fb9d61e7a3fb5eeb44e3a839
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83420
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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