diff options
| author | Yu-Ping Wu <yupingso@chromium.org> | 2024-07-25 17:44:53 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-07-26 07:23:34 +0000 |
| commit | 8e48f94b396f089d5b7a2d32b77ce5a71f9b2d97 (patch) | |
| tree | d3329d117596b37c0d362604455033299164d51b | |
| parent | 9c78a0e42263582bc91e5566fdfcb25eff7f23cc (diff) | |
soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START comment
Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/memlayout.ld | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld index 3dc386e1f4..732b5baeb6 100644 --- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld @@ -29,7 +29,7 @@ SECTIONS /* * The L3 is 2MB in total. The bootROM has configured half of the L3 cache as SRAM - *(SRAM_L2C) so that's 1MB (and the rest to be cache, which is required so you + * (SRAM_L2C) so that's 1MB (and the rest to be cache, which is required so you * can't reconfigure whole L3 as SRAM). */ SRAM_L2C_START(0x00200000) |