util/superiotool/fintek: Add f81866 register table

In accordance with the F81866A datasheet:
Release Date: Jan, 2012, Version: V0.14P [1].

[1] https://web.archive.org/web/20240707051837/http://www.
jetwaycomputer.com/download/Fintek/F81866_wdt_gpio.zip

Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83004
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 179 insertions, 0 deletions

diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c
index 035ec5f32d..390e8e38cf 100644
--- a/util/superiotool/fintek.c
+++ b/util/superiotool/fintek.c
@@ -10,6 +10,37 @@
 
 #define FINTEK_VENDOR_ID	0x3419
 
+/* f81866 Port Select (27h): BANK_PROG_SEL[3-2] CLK_TUNE_PROG_EN[0] */
+#define ESEL_27H(bank, en)	{.name = "Port Select Register", .idx = 0x27, .mask = 0x0d, \
+		.val = esel_27h_##bank | esel_27h_clk_tune_##en}
+/* f81866 Fan Fault Time Register (9Fh): FAN_PROG_SEL[7] */
+#define ESEL_9FH(bank)		{.name = "Fan Fault Time Register", .idx = 0x9f, .mask = 0x80, \
+		.val = esel_9fh_fan_prog_##bank}
+/* f81866 Block Write Count Register (ECh) ECh: MCH_BANK_SEL[7] */
+#define ESEL_ECH(data_temp)	{.name = "Block Write Count Register", .idx = 0xec, .mask = 0x80, \
+		.val = esel_ech_mch_bank_##data_temp}
+
+enum esel_27h_bank_prog_sel {
+	esel_27h_bank0 = 0 << 2,
+	esel_27h_bank1 = 1 << 2,
+	esel_27h_bank2 = 2 << 2,
+	esel_27h_bank3 = 3 << 2,
+};
+enum esel_27h_clk_tune {
+	esel_27h_clk_tune_dis = 0,
+	esel_27h_clk_tune_en  = 1,
+};
+
+enum esel_9fh_fan_prog {
+	esel_9fh_fan_prog_bank0 = 0 << 7,
+	esel_9fh_fan_prog_bank1 = 1 << 7,
+};
+
+enum esel_ech_mch_bank {
+	esel_ech_mch_bank_temp = 0 << 7,
+	esel_ech_mch_bank_data = 1 << 7,
+};
+
 static const struct superio_registers reg_table[] = {
 	{0x0106, "F71862FG / F71863FG", {	/* Same ID? Datasheet typo? */
 		/* We assume reserved bits are read as 0. */
@@ -450,6 +481,88 @@ static const struct superio_registers reg_table[] = {
 			{NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}},
 		{EOT}}},
 	{0x1010, "F81866", {
+		{NOLDN, NULL, /* Global Control Registers */
+			{0x02, 0x07, 0x20, 0x21, 0x23, 0x24, 0x25, 0x26, 0x27, 0x2d, EOT},
+			{NANA, 0x00, 0x10, 0x10, 0x19, 0x34, 0x00, 0x03, 0x00, 0x08, EOT}},
+		{NOLDN, NULL,
+			{0x27, 0x2d, 0x28, 0x29, 0x2a, 0x2b, 0x2c, EOT},
+			{0x00, 0x08, 0x60, 0x03, NANA, 0x02, NANA, EOT},
+			ESEL_27H(bank0, dis)}, /* selectable */
+		{NOLDN, NULL,
+			{0x27, 0x28, 0x2c, EOT},
+			{0x00, NANA, 0x0f, EOT},
+			ESEL_27H(bank1, dis)}, /* selectable */
+		{NOLDN, NULL,
+			{0x27, 0x2c, EOT},
+			{0x00, 0x00, EOT},
+			ESEL_27H(bank2, dis)}, /* selectable */
+		{NOLDN, NULL,
+			{0x27, 0x29, 0x2A, 0x2b, 0x2c, EOT},
+			{0x00, 0x03, 0xe7, NANA, NANA, EOT},
+			ESEL_27H(bank0, en)}, /* selectable */
+		{0x00, "FDC",
+			{0x30, 0x60, 0x61, 0x70, 0x74, 0xf0, 0xf2, 0xf4, EOT},
+			{NANA, 0x03, 0xf0, NANA, NANA, NANA, NANA, NANA, EOT}},
+		{0x03, "LPT",
+			{0x30, 0x60, 0x61, 0x70, 0x74, 0xf0, EOT},
+			{NANA, 0x03, 0x78, NANA, NANA, NANA, EOT}},
+		{0x04, "HWMON",
+			{0x30, 0x60, 0x61, 0x70, EOT},
+			{NANA, 0x02, 0x95, NANA, EOT}},
+		{0x05, "KBC",
+			{0x30, 0x60, 0x61, 0x70, 0x72, 0xfe, EOT},
+			{NANA, 0x00, 0x60, NANA, NANA, NANA, EOT}},
+		{0x06, "GPIO",
+			{0x30, 0x60, 0x61, 0x70, 0x71, 0x72, 0x73, 0x7e, 0x7f,
+			 0xf0, 0xf1, 0xf2, 0xf3, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, /* f0...f9 GPIO0 */
+			 0xe0, 0xe1, 0xe2, 0xe3, 0xe8, 0xe9, /* e0...e9 GPIO1 */
+			 0xd0, 0xd1, 0xd2, 0xd3, /* d0...d3 GPIO2 */
+			 0xc0, 0xc1, 0xc2, 0xc3, /* c0...c3 GPIO3 */
+			 0xb0, 0xb1, 0xb2, 0xb3, /* b0...b3 GPIO4 */
+			 0xa0, 0xa1, 0xa2, 0xa3, 0xa8,0xa9, /* a0...a9 GPIO5 */
+			 0x90, 0x91, 0x92, 0x93, /* 90...93 GPIO6 */
+			 0x80, 0x81, 0x82, 0x83, /* 80...83 GPIO7 */
+			 0x88, 0x89, 0x8a, 0x8b, 0x8e, 0x8f, /* 88...8f GPIO8 */
+			 EOT},
+			{NANA, 0x00, 0x60, NANA, NANA, NANA, NANA, 0x00, 0x00,
+			 0x00, 0x0f, NANA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* f0...f9 GPIO0 */
+			 0x00, 0xff, NANA, 0x00, 0x00, 0x00, /* e0...e9 GPIO1 */
+			 0x00, 0xff, NANA, 0x00, /* d0...d3 GPIO2 */
+			 0x00, 0xff, NANA, 0x00, /* c0...c3 GPIO3 */
+			 0x00, 0xff, NANA, 0x00, /* b0...b3 GPIO4 */
+			 0x00, 0xff, NANA, 0x00, 0x00, 0x00, /* a0...a9 GPIO5 */
+			 0x00, 0xff, NANA, 0x00, /* 90...93 GPIO6 */
+			 0x00, 0xff, NANA, 0x00, /* 80...83 GPIO7 */
+			 0x00, 0xff, NANA, 0x00, 0x00, 0x00, /* 88...8f GPIO8 */
+			 EOT}},
+		{0x07, "WDT",
+			{0x30, 0x60, 0x61, 0xf5, 0xf6, 0xfa, EOT},
+			{NANA, 0x00, 0x00, 0x00, 0x00, NANA, EOT}},
+		{0x0a, "PME, ACPI & ERP",
+			{0x30, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf8, 0xf9, 0xfa,
+			 0xfc, 0xfe, 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8,
+			 0xe9, 0xec, 0xed, 0xee, EOT},
+			{NANA, 0x00, NANA, 0x00, NANA, 0x07, 0x1c, 0x00, 0x00, 0x00, 0x07,
+			 0x00, 0x00, 0x0c, 0x00, 0x00, 0x13, 0x09, 0xc7, 0x13, 0x63, 0x10,
+			 0x0f, 0x14, 0x00, 0x00, EOT}},
+		{0x10, "UART1",
+			{0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT},
+			{NANA, 0x03, 0xf8, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}},
+		{0x11, "UART2",
+			{0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT},
+			{NANA, 0x02, 0xf8, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}},
+		{0x12, "UART3",
+			{0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT},
+			{NANA, 0x03, 0xe8, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}},
+		{0x13, "UART4",
+			{0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT},
+			{NANA, 0x02, 0xe8, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}},
+		{0x14, "UART5",
+			{0x30, 0x60, 0x61, 0x70, 0xf0, 0xf2, 0xf4, 0xf5, 0xf6, EOT},
+			{NANA, 0x00, 0x00, NANA, NANA, NANA, 0x00, 0x00, 0x00, EOT}},
+		{0x15, "UART6",
+			{0x30, 0x60, 0x61, 0x70, 0xf0, 0xf1, 0xf2, 0xf4, 0xf5, 0xf6, EOT},
+			{NANA, 0x00, 0x00, NANA, NANA, 0x04, NANA, 0x00, 0x00, 0x00, EOT}},
 		{EOT}}},
 	{0x0215, "F81962/F81964/F81966/F81967", {
 		{EOT}}},
@@ -508,6 +621,72 @@ static const struct superio_registers hwm_table[] = {
 			 NANA, NANA, NANA, NANA, NANA, 0x00, 0x01, 0x01,
 			 0x00, EOT}},
 		{EOT}}},
+	{0x1010, "F81866", {
+		/* 6.4.2.1 Configuration Setting */
+		{NOLDN, "General",
+			{0x01, 0x02, 0x03, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0f, 0xe0,
+			 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xec, 0xed,
+			 0xee, 0xef, EOT},
+			{0x03, 0x00, 0x00, 0x4c, 0x00, 0x10, 0x00, 0x55, 0x00, 0x00, 0x00,
+			 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
+			 0x01, 0x00, EOT}},
+		{NOLDN, "TSI/I2C",
+			{0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xec, 0xed,
+			 0xee, 0xef, EOT},
+			{NANA, NANA, NANA, NANA, NANA, NANA, NANA, NANA, NANA, 0x00, 0x00,
+			 0x01, 0x00, EOT},
+			ESEL_ECH(temp)}, /* selectable */
+		/* 6.4.2.3 PECI 3.0 & Temperature Setting */
+		{NOLDN, "PECI",
+			{0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a,
+			 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, EOT},
+			{0x00, 0x00, RSVD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			 0x00, 0x00, 0x00, 0x00, 0x00, EOT}},
+		{NOLDN, "Temperature Monitor",
+			{0x60, 0x61, 0x62, 0x63, 0x64, 0x66, 0x6b, 0x6c, 0x6d, 0x6f, 0x70,
+			 0x72, 0x73, 0x74, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x80, 0x81, 0x82,
+			 0x83, 0x84, 0x85, 0x7f, 0x8e, EOT},
+			{0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x44, 0x04, RSVD, RSVD,
+			 RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, 0x64, 0x55, 0x64,
+			 0x55, 0x64, 0x55, 0x00, 0xaa, EOT}},
+		/* 6.4.2.4 Voltage Setting */
+		{NOLDN, "Voltage Monitor",
+			{0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x3f, 0x20, 0x21,
+			 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+			 0x36, 0x37, 0x38, 0x39, 0x3a, EOT},
+			{0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, RSVD, RSVD,
+			 RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, 0x89, 0xf2,
+			 0xe2, 0xe1, 0x83, 0x96, 0xff, EOT}},
+		{NOLDN, "FAN Control", /* 6.4.2.5 Fan Control Setting - Control Setting */
+			{0x90, 0x91, 0x92, 0x93, 0x97, 0x98, 0x99, 0x9a, 0x9c, 0x9d, 0x9e,
+			 0x9f, EOT},
+			{0x00, RSVD, RSVD, 0x00, 0x00, 0x44, 0x02, 0x00, 0x55, 0x05, 0x66,
+			 0x0a, EOT},
+		},
+		{NOLDN, "FAN Control",
+			{0x94, 0x95, 0x96, 0x9b, 0x9f, EOT},
+			{0x00, NANA, 0x19, 0x19, 0x0a, EOT},
+			ESEL_9FH(bank0)}, /* selectable */
+		{NOLDN, "FAN Control",
+			{0x94, 0x95, 0x96, 0x9b, 0x9f, EOT},
+			{0x00, 0x00, 0x00, 0x19, 0x0a, EOT},
+			ESEL_9FH(bank1)}, /* selectable */
+		{NOLDN, "FAN1 Monitor", /* 6.4.2.5 Fan Control Setting - FAN 1,2,3 */
+			{0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa,
+			 0xab, 0xac, 0xad, 0xae, 0xaf, EOT},
+			{0x0f, 0xff, 0x00, 0x01, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff,
+			 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}},
+		{NOLDN, "FAN2 Monitor",
+			{0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba,
+			 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, EOT},
+			{0x0f, 0xff, 0x00, 0x01, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff,
+			 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}},
+		{NOLDN, "FAN3 Monitor",
+			{0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca,
+			 0xcb, 0xcc, 0xcd, 0xce, 0xcf, EOT},
+			{0x0f, 0xff, 0x00, 0x01, 0x03, 0xff, 0x3c, 0x32, 0x28, 0x1e, 0xff,
+			 0xd9, 0xb2, 0x99, 0x80, 0x1d, EOT}},
+		{EOT}}},
 	{EOT}
 };