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The FSP gets these values from the UPD and sets the internal values.
The document about eDP tuning is attached in issue tracker of this
ticket, at the issue tracker b/203061533#comment6.
BUG=b:203061533
Cq-Depend: chrome-internal:4303901
Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This reverts commit bd9b044a96cc ("mb/system76: rtd3: Remove SrcClk pin
on CPU RP").
Previously, RTD3 expected a PCH index for the root port and did not work
with the CPU PCIe RP present on TGL, so SrcClk pin was disabled.
Set them now that RTD3 supports mapping the index for the CPU RP.
Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Update DPTF settings provided by thermal team
BUG=b:215033682
TEST=build and tested on taniks board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic6860980b06e876dd4c21af26752ab6c1a3f7fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Taniks is going to exchange i2c port for touchscreen and cr50.
BUG=b:215039999
TEST=emerge-brya coreboot
Cq-Depend:chromium:3397562
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I179949887f6d8f4bbdff7d806319e2ac368ebc2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Taniks will use two PCIE port signals with one slot, one CLK and one
CLKREQ at next build. In order to accommodate this, probe statements
are added to the devicetree. This only affects NVME SSD and EMMC.
BUG=b:215040000
TEST=Build FSP with debug output enabled, and observe the correct root
ports being initialized depending on the FW_CONFIG values for BOOT_EMMC
and BOOT_NVME.
Cq-Depend:chromium:3397561
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2ead505088f19fd3bf9768b541838395c82ef051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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In order to guarantee data integrity an expired TCO must not hard reset
the board. Select the Kconfig switch to prevent this reset.
Change-Id: I04080c6bcd486e3a406438cc7a703165bb6945a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The TCO timer is the default watchdog of an x86 host and can reset the
system once it has expired for the second time. There are applications
where this reset is not acceptable while the TCO is used. In these
applications the TCO expire event generates an interrupt and software
takes care. There is a bit in the TCO1_CNT register on Elkhart Lake to
prevent this reset on expiration (called NO_REBOOT, see doc #636722 ).
This bit can either be strapped on hardware or set in this register to
avoid the reset on expiration. While the hardware strap cannot be
overridden in software, the pure software solution is more flexible.
Unfortunately, the location for this bit differs among the different
platforms. This is why it has to be handled on soc level rather than on
TCO common code level.
This commit adds a Kconfig option where NO_REBOOT can be enabled. This
makes it easy to reach this feature over to the mainboard where it can
be selected if needed.
Change-Id: Iaa81bfbe688edd717aa02db86f0a93fecdfcd16b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Prepares compilation for x86_64 by avoiding casts to different sizes.
Current patch fixes:
1.
src/northbridge/intel/i945/raminit.c: In function 'ram_read32':
src/northbridge/intel/i945/raminit.c:77:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
77 | read32((void *)offset);
| ^
2.
src/northbridge/intel/i945/rcven.c: In function 'sample_strobes':
src/northbridge/intel/i945/rcven.c:29:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
29 | read32((void *)addr);
| ^
src/northbridge/intel/i945/rcven.c:30:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
30 | read32((void *)(addr + 0x80));
| ^
3.
src/northbridge/intel/i945/gma.c: In function 'intel_gma_init_lvds':
src/northbridge/intel/i945/gma.c:98:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
98 | (void *)pgfx, mmiobase, piobase, pphysbase);
| ^
src/northbridge/intel/i945/gma.c:359:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
359 | (void *)pgfx, hactive * vactive * 4);
| ^
src/northbridge/intel/i945/gma.c:360:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
360 | memset((void *)pgfx, 0x00, hactive * vactive * 4);
| ^
src/northbridge/intel/i945/gma.c: In function 'intel_gma_init_vga':
src/northbridge/intel/i945/gma.c:384:17: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
384 | (u32)mmiobase, piobase, pphysbase);
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4.
src/northbridge/intel/i945/northbridge.c: In function 'mch_domain_read_resources':
src/northbridge/intel/i945/northbridge.c:64:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
64 | cbmem_topk = ((uint32_t)cbmem_top() / KiB);
| ^
Change-Id: I5ac7a1cb5d85a346114f909047d5a7c21ddb43e9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Chromebooks normally run with non-serial enabled firmware because
writing to the UART console is very slow. This unfortunately makes
debugging boot errors more difficult. We tend to rely on port 80s and/or
the vboot recovery code.
When CONSOLE_CBMEM_DUMP_TO_UART is selected it will dump the entire
cbmem console to the UART whenever `vboot_reboot()` is called. We don't
incur any boot time penalty in the happy path, but still retain the
ability to access the logs when an error occurs.
The previous implementation was using a hard coded UART index and
`get_uart_baudrate` was always returning 0 since `CONFIG_TTYS0_BAUD`
wasn't defined. This change makes it so the UART console properties are
available when CONSOLE_CBMEM_DUMP_TO_UART is set. This results in the
following .config diff:
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_TTYS0_BASE=0x3f8
+CONFIG_TTYS0_LCS=3
+CONFIG_CONSOLE_SERIAL_115200=y
+CONFIG_TTYS0_BAUD=115200
This functionality is especially helpful on Guybrush. PSP Verstage is
run on S0i3 resume. Today, if there is an error, the cbmem console is
lost since it lives in the PSP SRAM.
BUG=b:213828947, b:215599230
TEST=Build non-serial guybrush FW and verify no serial output happens in
happy path. Inject a vboot error and perform an S0i3 suspend/resume.
Verify CBMEM console gets dumped to the correct UART.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I997942204603362e51876a9ae25e493fe527437b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The FSP API is used to notify the FSP about different phases in the
boot process. The current FSP specification supports three notify
phases:
- Post PCI enumeration
- Ready to Boot
- End of Firmware
This patch attempts to make calling into the FSP Notify Phase APIs
optional by using native coreboot implementations to perform the
required lock down and chipset register configuration prior boot to
payload.
BUG=b:211954778
TEST=Able to build brya without any compilation issue and coreboot
log with this code changes when SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
and SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config enabled.
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Since Tiger Lake platform, the HECI1 device can be disabled on
Alder Lake platform using two different mechanism:
A. Using PMC IPC command 0xA9.
B. Sending SBI message under SMM.
In current scope of Alder Lake the default implementation is using
(B) sending sbi message under SMM. A follow up patch to add the
possible options and let platform to choose the applicable one.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1
device can undergo the PCI enumeration and later based on the
mainboard policy the HECI1 device can be disabled.
Mainboards that choose to make HECI1 enable during boot don't override
`DISABLE_HECI1_AT_PRE_BOOT` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable EC keyboard backlight for volmar.
BUG=b:211891086
TEST=FW_NAME=volmar emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I24ec7c8ca770cb438aabcf16b252032eef6d734d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update initial gpio configuration for volmar
BUG=b:211891086
TEST=FW_NAME=volmar emerge-brya coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I1bd3f1b3807b546d5a827ac89f0dc9bc8aaec40a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs.
Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548)
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Enable PSE GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Add PSE GBE ACPI devices
3. Refactor PCH GBE FSP-S code and merge it together
with PSE GBE code
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The Intel® Programmable Services Engine (Intel® PSE) is a
dedicated offload engine for IoT functions powered by an ARM
Cortex-M7 microcontroller. It provides independent, low-DMIPS
computing and low-speed I/Os for IoT applications, plus
dedicated services for real-time computing and time-sensitive
synchronization.
The PSE hosts new functions, including remote out-of-band
device management, network proxy, embedded controller lite
and sensor hub.
This CL enables the user to provide the base address of the
PSE FW blob which will then be loaded by the FSP-S onto the
ARM controller. PSE FW will do the initialization work of
PSE controller and its peripherals. The loading of PSE FW
should have negligible impact on boot time unless PSE
controller could not locate the PSE FW and FSP will attempt to
redo PSE FW loading and wait for PSE handshake until it times
out. Once PSE controller locate the PSE FW, it will do
initialization concurrently by itself with coreboot booting.
It also adds PSE related FSP-S UPD settings which enable the
setup of peripheral ownership (assigned to the PSE or x86
subsystem) and interrupts. These assignments need to take
place at a given point in the boot process and cannot be
changed later.
To verify if PSE FW is loaded properly, the user could enable
PchPseShellEnabled flag and the log will be printed at PSE UART
2.
For further info please refer to doc #611825 (for HW overview)
and #614110 (for PSE EDS).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Constructed out of a mix of autoport results, p8z77-m_pro, and
tool dumps.
Working:
- Core i7-3770K CPU
- SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903
(all further tests are under these versions)
- USB2 / USB3
- SATA
- Gigabit ethernet
- CPU temp sensors (memtest86+ 5.0.1)
- Hardware monitoring under Linux
- Native and MRC raminit
- PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600)
- Integrated graphics with Intel OpROM and libgfxinit (all ports)
- Serial port
- Windows with libgfxinit framebuffer
- 2ch sound playback, Linux and Windows
Not working:
- PS/2 mouse
- 6ch analog audio out
- PCI POST card in PCI slot
Untested:
- PS/2 keyboard
- Internal USB3 ports
- Digital audio out
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Fast-k flow may need to re-init header because mrc_cache doesn't
store header. Storing header together with dparam data is better
for data consistancy.
TEST=fast calibration pass on Corsola
BUG=b:204226005
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I22982923dce06c9e770aa4f20f3dcd2f33685d84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Check for situations where a Type C device isn't useful and avoid
creating one for those scenarios.
BUG=b:215199976
TEST=Tested on brya; verified that USBC device is created.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Tested-by: Alyssa Ross <hi@alyssa.is>
Change-Id: I5e1598bd637ec9f50e7bf8dab9e3c757a30b9848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Compared to Cezanne there are 3 more UARTs controllers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id98767197a21cb1a61f54fc9b256b10a9506c791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Compared to Cezanne there are 3 more UARTs with DMA controllers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a3d255bb4976a55623f3a161e791e80f1d01c69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Let's increase this to avoid losing any logs.
BUG=b:213828947
TEST=Boot guybrush and no longer see
*** Pre-CBMEM romstage console overflowed, log truncated!
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3258145e352af3a75893c7cc96f36eb238c99abb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Replace the Renoir/Cezanne PCI IDs with the Sabrina ones that were added
in commit 27b02c2eee68f4b6c8520c4737224aaaf81f137d (include/device/
pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I427df6f8e8c08fb47ae8513b6cf1085d4294e28f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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To have the new AMD Sabrina SoC code tested, add the AMD Chausie
mainboard as a copy of Majolica. This patch also changes the name from
Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC
and comments out the APCB_SOURCES since those aren't available in the
3rdparty/blobs repository yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Document #55758 Rev. 1.13 says that family 17h models 30h-3Fh and later
use the spi_readmode_f17_mod_30_3f struct element for SPI_MODE_FIELD and
spi_fastspeed_f17_mod_30_3f for SPI_SPEED_FIELD, so also use this for
The AMD Sabrina SoC which is family 17h models A0h-AFh.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I336f9ea4a0defdf34e1af4b6d568cfe46488f75e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The Cezanne SoC code was initially started as a copy of example/min86
which only provides enough code to make the SoC code build. Then the
different parts of the real SoC support was brought in patch by patch
which also helped cleaning up and untangling the code. Since the Cezanne
SoC code is now in a rather good shape and the Sabrina SoC is similar to
the Cezanne SoC from the coreboot side, the new SoC support is started
with a copy of the Cezanne code and all the needed changes will be
applied on top of that. In order for the build not to fail due to
duplicate files, this patch does not only copy the directory, but also
replaces most instances of the Cezanne name with Sabrina. Since the
needed blobs aren't available in the 3rdparty/amd_blobs repository yet,
the Cezanne blobs are used for now so that the build will succeed. As
soon as the proper blobs will be available in that repository, the code
will be switched over to use them.
As suggested by Nico, I added a "TODO: Check if this is still correct"
comment to the beginning of every copied file and all SOC_AMD_COMMON_*
Kconfig option selects which will be removed after re-verifying that
each file and each selected common code block is still correct for the
new SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The AMD Sabrina SoC will be using the FSP driver to call into the
corresponding FSP binary to do its part of for the silicon
initialization, so we need an initial set of FSP headers for the AMD
Sabrina SoC code to build. Since the FSP interface for this SoC won't be
too different from the Cezanne FSP interface, we'll start with a copy of
the Cezanne FSP headers and update/replace them as soon as the proper
FSP headers for Sabrina will be available.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib3bf50598efe60673b81cf99da491866fb5dc121
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add I2C bus for banshee in Kconfig
BUG=b:214871796
TEST=emerge-brya coreboot
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I67592051b367d5a5715f8d1253ea0c11d2deb1c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Update override devicetree based on schematics
BUG=b:214871796
TEST=emerge-brya coreboot
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I05b63ebcded2f37dfb0f6c428e1fb993f476006a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This reverts commit 2a8de6dafb7eec8ff9112b43888507fbc0d8f851.
SeaBIOS 1.15.0 regresses on systems with NVMe devices [1]:
> Greetings! Was this patch set tested on bare metal hardware? I'm
> seeing "GRUB loading: Read Error" when attempting to boot from NVMe on
> various Purism Librem devices (Intel Skylake thru Cometlake hardware).
> Reverting this series resolves the issue.
So, revert back to SeaBIOS 1.14.0.
[1]: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/message/SRECAGH4NE3XPDWJ2YI526L5LPSJWENJ/
Change-Id: If2ec738d478f11b203f499eaa28197357de6630d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61179
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The object pointed to by the struct device * argument is not modified,
therefore it can be made const.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I300d2a59eb0513ddd08d4f1d2a3c6eb829e3f836
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I624dd67b6ce9b87a6031b5467eacb9a8d7cda1cd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Modify i2c signal to meet touchpad vendor spec.
Please see issue tracker for more details.
BUG=b:215487482
TEST=emerge-brya coreboot and check measured waveform in spec
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib3797d4e232654ada97092d9f2742ca040d0f0e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The Lemur Pro, with its mixed memory topology, only has a DIMM at
address 0x52.
Change-Id: Iecea8c70c7fd40943d86f8918f8e3b384538b5c3
Fixes: 4dcee4f21db5 ("mb/system76/lemp10: Add System76 Lemur Pro 10")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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When calling get_pcie_rp_pmc_idx(), the following code checked the
return value to see if it was negative or `> CONFIG_MAX_ROOT_PORTS`.
However, the expected return value for CPU PCIe RPs is above
MAX_ROOT_PORTS. Since the static, local function is intended to return
-1 or a valid value, drop the check for `> CONFIG_MAX_ROOT_PORTS`.
Change-Id: I2039273ad246884cd8736a7f0355e621a706a526
Fixes: b6a15a7 ("soc/intel/common/block/pcie/rtd3: Update ACPI Update
ACPI methods for CPU PCIe RPs")
Tested-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Change-Id: I909f74853a37a783582471e05071bc3d07e3dcf8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Like the variant function to change DXIO settings, add a similar weak
function to modify the DDI settings.
Currently we follow the old way. Later we will find out a better way
to avoid using weak function.
Change-Id: I9898d717bc3025ea1ddc3b0db41325083324ed57
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
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To be shared with different SOCs, move the dramc_param_header struct
as well DRAMC_PARAM_FLAG and DRAMC_PARAM_CONFIG enums to a common
header file dramc_param_common.h.
TEST=fast calibration pass
BUG=b:204226005
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I087971799803e47e34c30063b2b0bd0cfc5795ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61132
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Building libgfxinit with Debian’s toolchain – latest test with *gnat-11*
11.2.0-13 from Debian sid/unstable – the build fails with the error
below.
E: Invalid reloc type: 10
E: Unable to create rmodule from 'build/cbfs/fallback/ramstage.debug'.
Debian’s toolchain is built without enabling PIE by default.
So, explicitly pass `-fno-pie` to `ADAFLAGS_common` to be independent
from how the toolchain was built.
TEST=*gnat* 11.2.0-13 successfully. builds
purism/librem_cnl/variants/librem_mini with libgfxint.
With the coreboot toolchain `make BUILD_TIMELESS=1` produces the
same `build/coreboot.rom` for `BOARD_PURISM_LIBREM_MINI_V2=y` on
top of commit 50251400d2 (sb/intel/common/firmware: Reword
me_cleaner warning) with and without the change.
Change-Id: I6661937906d95c130c6099f598d61b21e958fd85
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This change splits the size of the console transfer region and size of
the bootblock/romstage Pre-RAM console region. This allows having a
larger Pre-RAM console while not impacting the size of the PSP verstage
console.
Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in
`setup_cbmem_console`, I chose to use the offsets provided in the
transfer buffer. It would be nice to eventually do this for all the
fields in the transfer buffer.
BUG=b:213828947
TEST=Boot guybrush and verify verstage logs are no longer truncated
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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When running in verstage before bootblock, the PSP (ARM co-processor) is
running with limited SRAM. It needs to stash the verstage console data
internally until DRAM is brought up. Once DRAM is brought up the data is
stashed in a "transfer buffer" region. In the current design, we are
using the same region for the transfer buffer and the
preram_cbmem_console region. This has the following downsides:
1) The pre-x86 buffer needs to be large enough to hold all the
verstage, bootblock and romstage console logs.
2) On AMD platforms, the PSP verstage is signed. Changing the size of
preram_cbmem_console after the fact will result in a mismatch of the
transfer buffer between verstage and bootblock.
This CL adds a new method that allows SoC specific code to copy the
CBMEM console in the transfer buffer to the active CBMEM console.
BUG=b:213828947
TEST=Boot guybrush and no longer see
*** Pre-CBMEM romstage console overflowed, log truncated!
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc0ab8090db740e0d1b3d21d8968f26471f2e930
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Fixes commit 6bcaf6f (mb/system76/lemp9: Configure IRQs as level
triggered for HID over I2C), which changed the interrupt configuration
in the device tree but not in the GPIO definitions. Tested on a
System76 Lemur Pro (lemp9), multi-touch I2C-HID was working.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I7f0559675a65453a1ad071f96049549a2dc21378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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BUG=b:198258604
BRANCH=guybrush
TEST=emerge-guybrush coreboot
WLAN works properly in OS
Change-Id: Ie1f295eaa57af7c2942e1807b3a0c4dcd89cd696
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I79f2206bee5403c3fb1c999918fbd2177d0d07ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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The patch implements get_soc_cpu_type() helper function which
determines whether the executing CPU is a small or a big core. This is
the SoC-specific callback that must be implemented for SoCs that select
SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID. It will be called from
set_cpu_type().
TEST=verified on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Icd0d7e8a42c4b20d3e1d34998bca6321509df2d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:182575295
TEST=Boot to OS, check cbmem -t
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 80,408
945:CSE started to handle ICC configuration 80,408 (0)
946:CSE sent 'Host BIOS Prep Done' to PMC 82,408 (2,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC 242,408 (160,000)
0:1st timestamp 331,797 (89,389)
11:start of bootblock 359,484 (27,686)
12:end of bootblock 377,417 (17,932)
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9e4ccd0b8c301e4eec1a09ee8919a577ade938ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Rebase all of the timestamps to the lowest (potentially negative) value
in the list when displaying them. Also drop the extra
`timestamp_print_*_entry` calls for time 0 and instead inserted a
"dummy" timestamp entry of time 0 into the table.
TEST=Boot to OS after adding negative timestamps, cbmem -t
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I7eb519c360e066d48dde205401e4ccd3b0b3d8a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change timestamp_add to accept negative values for events that took
place before coreboot started executing.
TEST=Boot to OS, check cbmem -t
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I90afc13a8e92693d86e3358f05e0a0cb7cdbca9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This command retrieves a set of boot performance timestamps
CSME collected during the platform's last boot flow.
BUG=b:182575295
TEST=Verify CSME timestamps after S3 and boot.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reverts commit 6a3bdf9aa5da6b620952c915330ce70702735456.
Reason for revert: Oops, I thought I abandoned this. It's been replaced by https://review.coreboot.org/c/coreboot/+/61099/3
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id18e8e69481bdd78fdd70116940ea435922a9e77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Tested by checking PCR-2 data is recorded in cbmem log.
Change-Id: I70cb9a93de44e75f3a3ed24979c243fccea1213d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Update GPIO settings as per schematics v3.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I685d0b7274e3a6e707fec37d051f4818860169ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The _UID must be unique as these devices use the same _HID. Fixes BSOD
when booting Windows 10.
Change-Id: I67fda892a496dc9e5a6fa5e133ff0b35cde8fce7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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We set T3 as 300ms to meet Elan's spec, but the resume/suspend times
are greater than 500ms, which is the spec for Chromebooks.
The actual kernel timing has been measured, and given the ACPI delay
after deasserting reset in addition to the delay until the kernel
driver accesses the device, delaying only 200ms in the ACPI method is
also sufficient to meet the 300ms requirement.
BUG=b:210772498
BRANCH=none
TEST=build and test touchscreen function on DUT.
TEST=suspend, wake DUT and check touchscreen function.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I4bb4eda09686cb59b6e19c741aa2b78d84332d2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch provides the possible options for PCH to allow `Pad
Configuration Lock`.
`SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI` config is for Tiger Lake
Point (TGP) and Alder Lake Point (ADP) PCH.
BUG=b:211573253, b:211950520
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7cf35893ab613b154a1073060081a09e561ffe56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch introduces a `const bit_mask` variable to hold the gpio
PAD mask value prior to sending the lock configuration command using
the sideband interface.
Additionally, this patch fixes the PAD lock overridden issue as below:
Without this code change every consecutive PAD lock operation resets
other bits in that register as below:
After Locking pad 2 , pcr_read=0x4
After Locking pad 3 , pcr_read=0x8
After Locking pad 4 , pcr_read=0x10
After Locking pad 5 , pcr_read=0x20
After Locking pad 6 , pcr_read=0x40
After Locking pad 7 , pcr_read=0x80
After Locking pad 8 , pcr_read=0x100
With this code change all previous lock bits are getting preserved as
below:
After Locking pad 2 , pcr_read=0x4
After Locking pad 3 , pcr_read=0xc
After Locking pad 4 , pcr_read=0x1c
After Locking pad 5 , pcr_read=0x3c
After Locking pad 6 , pcr_read=0x7c
After Locking pad 7 , pcr_read=0xfc
After Locking pad 8 , pcr_read=0x1fc
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I342a666aa2d34bcc8ba33460396d1248f0c0f89f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60999
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ADL-P 2+8+2 (28W) would have a match PD to ADL-P 4+8+2 (28W). Group them
into the same group core "ADL_P_282_482_28W_CORE".
BUG=b:211365920
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I3f92c0f5d717dd33ac478fbaa883f3e972e7a7de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Camera LED blinks as sensor is being probed during kernel boot,
which misleads user to belive camera has been turned on.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:214155527
TEST=Build and boot Kano to OS. Verify entries in SSDT and monitor LED
during boot.
Signed-off-by: Jim Lai <jim.lai@intel.com>
Change-Id: I92f1e88d0fcce49660a95d4402c8c4161e320168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61109
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:210501484
BRANCH=puff
TEST=build
Change-Id: I84bc378d6b00828366309be7dbf56a61702a14da
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
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This will make the method available earlier. This is needed for the next
CL.
BUG=b:213828947
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iee911a2debcfbf4309d2e866401b74f2a6c18feb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The only option to make HECI1 function disable on Elkhart Lake SoC
platform is using SBI under SMM mode.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
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The only option to make HECI1 function disable on Ice Lake SoC
platform is using SBI under SMM mode. Hence, this patch makes
DISABLE_HECI1_AT_PRE_BOOT=y default and selects
`HECI_DISABLE_USING_SMM` config for Ice Lake.
Also, drop `HeciEnabled` from chip configuration and guard
heci_disable() using DISABLE_HECI1_AT_PRE_BOOT config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I837e1f8727adefb9227ac7df2ff715245957be2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61258
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This implementation is the same for all SoC that select
SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR
CPU support code folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I393feab8550a7124ab2982ff3d256e3491d27b4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This will verify that signed verstage binaries and the bootblock code
executing agree on the transfer buffer struct size.
BUG=b:213828947
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I597e38fe0a37416ffd3bc01fd974fa8f6610a88c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Configure GPIOs according to schematics
BUG=b:214871796
TEST=emerge-brya coreboot
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Id6862ff442310953b4749cef7880814f3c3f6d60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Banshee will use SODIMM. Add memory.c to override baseboard.
BUG=b:208910227
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I4d2fe986b786b3553b67910b589fce12647ee69a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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MEMORY_SOLDERDOWN puts SPD in cbfs and read part number from CBI.
MEMORY_SODIMM puts SPD cache in FMAP.
BUG=b:208910227
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idab48293fb5b584ecb4c8f270d2c376456954553
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Create the banshee variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:214871796
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_BANSHEE
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ib4f943a109f945204a9b0a8de9b99580bf01c87e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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llvm-ar does not support "open" script command, and fails with an error.
This patch fixes it by removing lines `$(AR) rc <object-files>` and
it puts them as "addmod" commands. This way all object files and
archives can be packed into one archive.
Change-Id: I0c53d1d613b5edc321e268d1d996fac3146680f8
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ie09e337ee1790a06689681fca087edcfd89d215f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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set_cpu_type(): It determines the CPU type (big or small) that
is executing the function, and marks the global_cpu_type's array slot
which is corresponds to the executing CPU's index if the CPU type is
big core.
get_cpu_index(): It determines the index from LAPIC Ids. This is
required to expose CPPC3 package in ascending order of CPUs' LAPIC ids.
So, the function returns CPU's position from the ascending order list
of LAPIC ids.
TEST=Tested CPU index calculation, core type determination on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add file gpio.c in romstage.
BUG=b:213828931
TEST=Build FW and system can power on normally.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ie868fe7ada9deb8918d6c7ba538332cbe539ee44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I58419450dbe34741b4f5b4920f435fdb91e9df22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I8567a567d979bcc0c1c710f6f231d7ecdc82b126
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch implements a SoC overrides to check CPU privilege level
as the MSR is not consistent across platforms.
For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR
0x151.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch creates a `relative increment by 1` macro to let SoC
gpio pad configuration to be more flexible while adding support
for newer PCH SoC.
With this changes adding GPIO controller support for PCH-N would
become really simple without too much of code duplication.
For example: ADL-N has added `GPP_I` pins into community 1 hence,
the additional code for `PCH-N` whould appear incremetal to ADL-P.
> #define GPP_B 0x0
> #define GPP_T INC(GPP_B)
> #define GPP_A INC(GPP_T)
> #define GPP_R INC(GPP_A)
> #define GPD INC(GPP_R)
> #define GPP_S INC(GPD)
> if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
> #define GPP_I INC(GPP_S)
> #define GPP_H INC(GPP_I)
> #else
> #define GPP_H INC(GPP_S)
> #endif
> #define GPP_D INC(GPP_H)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie3b2183381b877da0a6e5a27f5176f0e21e0c9fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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BUG=b:211528578
TEST=emerge-cherry coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I3bd9803b4e47882df9fe351229478e4cb1630363
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Present the Semtech SX9360 SAR sensor that protects the LTE antenna.
The sensor is connected to i2c bus I2C1.
BUG=b:194318328
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59609
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add driver for setting up Semtech sx9360 SAR sensor.
The driver is based on sx9310.c. The core of the driver is the same, but
the bindings are slightly different.
Registers are documented in the kernel tree:
Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
[https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/]
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This adds the following commits:
* 22ce1b5 cezanne: Upgrade SMU to 64.60.0
* dd37ad2 cezanne: Update ABL to 0x1B096070
* 01fbf5d cezanne: Update SMU to 64.58.0
* f638765 cezanne: Update ABLs to 0x1A296070
BUG=none
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f51cb007ce4127428b7b81095fb2c7afb33e608
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This will help debugging verstage failures.
BUG=b:213828947
TEST=Boot guybrush and verify verstage logs are printed before bootblock
messages.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia60991b3e81c19c24ceb69193840dde873ef3346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable S3/S0ix wake events for AC connect/disconnect on Alder Lake RVP.
BUG=None
BRANCH=None
TEST=Verify board wakes from S0ix on AC connect/disconnect.
Change-Id: Iaf92821fd69a59624e58cb8af3896e2b6998723f
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Add eMMC device into chipset.cb and keep it `off` by default.
eMMC device is applicable only for Alder Lake N SOC.
Change-Id: I2bc38ee5814688409feb7e4531c1daa5b54953c0
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Add eMMC device ID for Alder Lake N SOC.
Reference: Alder Lake N Platform EDS Volume 1 (Doc# 645548)
Change-Id: Id35ec2d508bec8ff7d6f1c5fbfaf209d42b25c72
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH:
in RW).
BRANCH=None
BUG=None
TEST=Issue manual recovery and confirm DUT is entering recovery mode.
Change-Id: Ib8b6be9fcda24bd2bb479b5b6c01f24a6e9c7b1f
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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The patch moves the CPPC_PACKAGE_NAME macro definition from file
acpi/acpigen.c to include/acpi/acpigen.h file since the
CPPC_PACKAGE_NAME method will get called from cpu/intel/common
in a later patch.
TEST=Built the code for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch
turns on I2C1 and turns off I2C3.
BUG=b:211886429
TEST=Test if proto 1 can boot into Chrome OS successfully.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I0e94c900b48adf10880aae2abb47e08d1bd9e19b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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This patch fixes the indentation issue introduced with commit 0c1c2dec
(Documentation: Capture anomalies between pad and lock reset type).
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib6974cda26e6f7968688a2a7c30c7351d212a780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Host device id 0x4619 is missed in few coreboot tables so that
coreboot can't recognize and config it properly.
Document Number: 690222
BUG:b:214665785, b:214680767
Change-Id: I95908bdc0a736bafedb328dda2a00b5473de3d88
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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That vendor firmware still works after applying `me_cleaner` doesn't
mean that coreboot will also work with the same broken ME firmware.
Instead, one should first test coreboot with the original, unmodified ME
firmware to make sure coreboot works properly, and only then consider
using `me_cleaner` with coreboot. Otherwise, one would end up with a
non-booting or otherwise misbehaving system when trying to use coreboot
and `me_cleaner` without having tested coreboot with the original ME
firmware beforehand, which is hard to diagnose as the problem may only
happen when the ME isn't running normally.
Change-Id: I1626d747a99969faf7db37c10cf7d87e3977744a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Updating from commit id 4c21b57eb:
2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions)
to commit id e486b388a:
2022-01-12 21:11:11 +0000 - (zephyr: Update power policy for API change)
This brings in 2212 new commits.
Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: I4437f09c3193ec7c89f7f9550940a0fa5464a511
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Thejaswani Putta <theja427@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
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In https://crrev.com/c/3069716, the samus EC firmware was removed from
the `main` branch, therefore in order to update the `chromeec` 3rdparty
submodule, the automatic build and inclusion of samus EC firmware into
coreboot's `master` branch has to be dropped as well.
Change-Id: I6fcdd3b7925b6ec33ba48892ed750c29bb60634c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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Turns out 150ms isn't enough in the worst reset conditions. On guybrush
the TPM is reset in S0i3 and the CR50 is allowed to hibernate. The CR50
is woken up and initialized early during S0i3 resume. Occasionally the
CR50 isn't ready before the probe times out.
BUG=b:213828947
BRANCH=None
TEST=suspend_stress_test -c 1000
Change-Id: Ifda438080cf1ad2796c7061223a6a97b8e6e9987
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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FSP 2.3 specification introduces following changes:
1. FSP_INFO_HEADER changes
Updated SpecVersion from 0x22 to 0x23
Updated HeaderRevision from 5 to 6
Added ExtendedImageRevision
FSP_INFO_HEADER length changed to 0x50
2. Added FSP_NON_VOLATILE_STORAGE_HOB2
Following changes are implemented in the patch to support FSP 2.3:
- Add Kconfig option
- Update FSP build binary version info based on ExtendedImageRevision
field in header
- New NV HOB related changes will be pushed as part of another patch
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU
PCIe UPDs), we need to set cpu pcie rp flags in devicetree now.
This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in
all intel projects or system will be blocked at PKGC2R with root port
LTR not enable.
BUG=b:214009181
TEST=Build and DUT (Kano) can enter deeper PKGC state normally.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Some SKUs of google/taeko4es have a Bayhub LV2 card reader chip,
therefore enable the corresponding driver for the mainboard.
BUG=b:204343849
TEST=Build FW and checking SD card reader register is correct.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I3d2ea3db9df38e7b0cac4c32e1fca579ff43e5bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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When using the default initial core display clock frequency (648MHz),
Jasper Lake board might have a rare stability issue where the startup
of Chrome OS in secure mode may hang during re-initializing display in
kernel graphic driver.
Bugzzy didn't show this problem so far, but Intel recommends slowing
the initial core display clock frequency down to 172.8 MHz to prevent
this potential problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0
(172.8 MHz) for bugzzy.
BUG=None
BRANCH=dedede
TEST=Build firmware and check the DUTs can boot up in secure mode well.
Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Align Denverton PCI ID define names with other Intel SoCs. Also,
update the names in SoC code accordingly.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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