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authorAnil Kumar <anil.kumar.k@intel.com>2021-11-11 18:56:21 -0800
committerFelix Held <felix-coreboot@felixheld.de>2022-01-17 15:53:28 +0000
commit57309d362cbd00b63f77d839a09dba58eb558615 (patch)
tree187b0a097e2d8aeeb2fdfad02c46235a1fa840b3
parentec877d633d0db3b40c28d2ef198313ab688cd3d4 (diff)
drivers/intel/fsp2_0: Add FSP 2.3 support
FSP 2.3 specification introduces following changes: 1. FSP_INFO_HEADER changes Updated SpecVersion from 0x22 to 0x23 Updated HeaderRevision from 5 to 6 Added ExtendedImageRevision FSP_INFO_HEADER length changed to 0x50 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 Following changes are implemented in the patch to support FSP 2.3: - Add Kconfig option - Update FSP build binary version info based on ExtendedImageRevision field in header - New NV HOB related changes will be pushed as part of another patch Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
-rw-r--r--src/drivers/intel/fsp2_0/Kconfig10
-rw-r--r--src/drivers/intel/fsp2_0/header_display.c16
-rw-r--r--src/drivers/intel/fsp2_0/include/fsp/info_header.h1
-rw-r--r--src/drivers/intel/fsp2_0/include/fsp/util.h8
-rw-r--r--src/drivers/intel/fsp2_0/util.c6
5 files changed, 35 insertions, 6 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index a0e02a83ca..716e809bf6 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -29,6 +29,16 @@ config PLATFORM_USES_FSP2_2
3. Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP2.0/2.1 can disable
the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change.
+config PLATFORM_USES_FSP2_3
+ bool
+ default n
+ select PLATFORM_USES_FSP2_2
+ help
+ Include FSP 2.3 wrappers and functionality.
+ Features added into FSP 2.3 specification that impact coreboot are:
+ 1. Added ExtendedImageRevision field in FSP_INFO_HEADER
+ 2. Added FSP_NON_VOLATILE_STORAGE_HOB2
+
if PLATFORM_USES_FSP2_0
config PLATFORM_USES_FSP2_X86_32
diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c
index 4f9366657d..4c8085ed65 100644
--- a/src/drivers/intel/fsp2_0/header_display.c
+++ b/src/drivers/intel/fsp2_0/header_display.c
@@ -6,16 +6,22 @@
void fsp_print_header_info(const struct fsp_header *hdr)
{
union fsp_revision revision;
+ union extended_fsp_revision ext_revision;
+ ext_revision.val = 0;
- revision.val = hdr->fsp_revision;
+ /* For FSP 2.3 and later use extended image revision field present in header
+ * for build number and revision calculation */
+ if (CONFIG(PLATFORM_USES_FSP2_3))
+ ext_revision.val = hdr->extended_fsp_revision;
+ revision.val = hdr->fsp_revision;
printk(BIOS_SPEW, "Spec version: v%u.%u\n", (hdr->spec_version >> 4),
hdr->spec_version & 0xf);
printk(BIOS_SPEW, "Revision: %u.%u.%u, Build Number %u\n",
- revision.rev.major,
- revision.rev.minor,
- revision.rev.revision,
- revision.rev.bld_num);
+ revision.rev.major,
+ revision.rev.minor,
+ ((ext_revision.rev.revision << 8) | revision.rev.revision),
+ ((ext_revision.rev.bld_num << 8) | revision.rev.bld_num));
printk(BIOS_SPEW, "Type: %s/%s\n",
(hdr->component_attribute & 1) ? "release" : "debug",
(hdr->component_attribute & 2) ? "official" : "test");
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
index 5b6318cb7c..136fc2b7a3 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -14,6 +14,7 @@
#if CONFIG(PLATFORM_USES_FSP2_X86_32)
struct fsp_header {
uint32_t fsp_revision;
+ uint16_t extended_fsp_revision;
uint32_t image_size;
uint32_t image_base;
uint16_t image_attribute;
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index d05b644886..7347034550 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -60,6 +60,14 @@ union fsp_revision {
} rev;
};
+union extended_fsp_revision {
+ uint16_t val;
+ struct {
+ uint8_t bld_num;
+ uint8_t revision;
+ } rev;
+};
+
#if CONFIG_UDK_VERSION < CONFIG_UDK_2017_VERSION
enum resource_type {
EFI_RESOURCE_SYSTEM_MEMORY = 0,
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
index 49934fe6de..ff79fc7715 100644
--- a/src/drivers/intel/fsp2_0/util.c
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -14,7 +14,9 @@
static uint32_t fsp_hdr_get_expected_min_length(void)
{
- if (CONFIG(PLATFORM_USES_FSP2_2))
+ if (CONFIG(PLATFORM_USES_FSP2_3))
+ return 80;
+ else if (CONFIG(PLATFORM_USES_FSP2_2))
return 76;
else if (CONFIG(PLATFORM_USES_FSP2_1))
return 72;
@@ -70,6 +72,8 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob)
hdr->silicon_init_entry_offset = read32(raw_hdr + 68);
if (CONFIG(PLATFORM_USES_FSP2_2))
hdr->multi_phase_si_init_entry_offset = read32(raw_hdr + 72);
+ if (CONFIG(PLATFORM_USES_FSP2_3))
+ hdr->extended_fsp_revision = read16(raw_hdr + 76);
return CB_SUCCESS;
}