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2023-04-29mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startupTarun Tuli
Add functionality to ensure that the FPMCU is power cycled long enough on boot to ensure proper reset. This solution relies solely on coreboot to sequence the power and reset signals appropriately (150ms on boot). -Confirmed power is off for 150ms on boot. -Confirmed RCC_CSR of FPMCU indicates power cycle occurred. -Confirmed reset is de-asserted approx 3ms after power application (target >2.5ms) BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami and timings are as expected. Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29mb/google/poppy: Add support for variant SKU romstage GPIO configsTarun Tuli
Add functionality that allows a variant SKU to have a specific set of GPIO configs in romstage (modeled after the existing one in ramstage) BUG=b:245954151 TEST=builds Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29mb/google/rex/variants/screebo: Generate RAM IDsKapil Porwal
Generate RAM IDs for - MT62F512M32D2DR-031 WT:B (LP5) H9JCNNNBK3MLYR-N6E (LP5) MT62F1G32D2DS-026 WT:B(LP5x) H58G56BK7BX068 (LP5X) BUG=b:276814951 TEST=Run part_id_gen tool without any errors Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74802 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29sb,soc/amd,intel: Drop include <cpu/x86/smm.h>Kyösti Mälkki
I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT entries for SMI architectural"). Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-28soc/amd/phoenix: Populate type 0x63 entry with right MRC CacheFred Reitberger
On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS directory entry in RO with that section. If the RECOVERY_MRC_CACHE section is not present, then fall back to RW_MRC_CACHE. BUG=b:270569389 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR windowFelix Held
This ports back commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0 BAR window") to Stoneyridge so that the correct end of the non-fixed MMIO region gets reported in PCI0's _CRS method. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/74809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI busesFelix Held
This ports commit 8c28e51a16e1 ("soc/amd/picasso: fix host bridge bus numbers") back to Stoneyridge so that the correct number of PCI buses gets reported from PCI0's _CRS method. The MCFG ACPI table already had the correct last bus number. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28mb/starlabs/starbook/adl: Correct the number of NID entriesSean Rhodes
The number of NID entries was too high for the Realtek and Intel sound cards, preventing the verb table from loading. Now the values are correct; it loads as intended. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-28ec/starlabs/merlin: Change the fallback value for fn_ctrl_swapSean Rhodes
Change the fallback value of the `fn_ctrl_swap` option to 0, which is disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9fcbb497f14ed0c97ff05c6c01a3929522786781 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28ec/starlabs/merlin/acpi: Don't attempt to change EC valuesSean Rhodes
The EC will constantly update the battery variables approximately every 60 seconds; they should be used unmodified, rather than trying to change them. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3cff0ac6a322018cbca33b5f90dd62b3475da25c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28mb/starlabs/starbook/adl: Correct port for Hot PlugSean Rhodes
Commit 5103b87a4d7b ("mb/starlabs/starbook/adl: Add an option to enable Hot Plug") introduced an option to enable Hot Plug for the SSD. The port was set to 4 (RP5) which is the wireless card. Change this to 8 (RP9) which is the SSD. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I884f4997d73e31bd422477952466f168afad66a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28amdfwtool: Increase MAX_PSP_ENTRIESFred Reitberger
The MAX_PSP_ENTRIES constant reserves space for the psp directory table entries. This table is aligned to 4K and the next binary is also aligned to 4K. The number of psp directory entries on Birman exceeds the previous limit, so increase it to the maximum that will fit in a 4K block. TEST=timeless builds for Birman unchanged Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I297edc9cccffde0ad1ce7461b375542f9f2f7c23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-28soc/intel/common/block/pmc: Sort Kconfig in alphabetical orderChristian Walter
Change-Id: I7392ede4226a940896c805fc0b0bc0dd615a964c Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74810 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-28treewide: Add missing include guards to chip.hJan Samek
Some of the chip.h files in the tree are missing the include guards. This patch adds them in order to avoid potential redefinions of symbols contained in these headers, when they are included multiple times in static.c generated by sconfig. Change-Id: I550a514e72a8dd4db602e7ceffccd81aa36446e3 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-28mb/google/rex/var/screebo: Add initial setup for gpio configKun Liu
add the initial gpio configuration for screebo initial variant BUG=b:276814951 TEST=emerge-rex coreboot Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74475 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-28vga: Change the arguments of vga_write_text to support extended ASCIIHsuan Ting Chen
VGA defined the extended ASCII set based on CP437, but the function vga_write_text() accepts a signed char array. This will cause unnecessary confusion that if we want to print u with umlaut (code=129 in CP437), we need to explicitly cast it to -127 in signed char. Since we still want to leverage the built-in string utilities which only accepts const char*, we still need to cast it to signed char while processing, and cast it back to unsigned once we write into the frame buffer. BRANCH=brya BUG=b:264666392 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-28mb/google/skyrim: Enable SPL fusing on MarkarthJohn Su
Because SPL fuse needs to be set before the FW lock. So enable Markarth project to send the fuse SPL (security patch level) command to the PSP. BUG=b:279499511 BRANCH=none TEST=FW_NAME="Markarth" emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I8fbbd89d11b1bdb2c95c761955c10bedb366fd70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74753 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27arch/x86: Disable walkcbfs_asm code when CONFIG_CBFS_VERIFICATION is setJulius Werner
walkcbfs_asm is a simple CBFS implementation in assembly to find a file on a system with memory-mapped SPI flash. It seems to be mostly unused nowadays and is only still called for early microcode loading on some old systems (e.g. FSP 1.1 and older). Using this implementation with CONFIG_CBFS_VERIFICATION is unsafe because it does not verify the hashes the way the normal CBFS code does. Therefore, to avoid potential security vulnerabilities from creeping in, this patch makes sure the code cannot be compiled in when CBFS_VERIFICATION is active. That means it won't be supported on the old boards using this for microcode loading. Ideally CONFIG_CBFS_VERIFICATION should have a `depends on` to make this dependency more obvious in menuconfig, but the configs actually using this code are not easy to untangle (e.g. CONFIG_MICROCODE_UPDATE_PRE_RAM is just set everywhere by default although only very few boards are really using it, and a lot of different old Intel CPU models are linking in src/cpu/intel/car/non-evict/cache_as_ram.S without being united under a single Kconfig so that's not easy to change). To keep things simple, this patch will just prevent the code from being built and result in a linker error if a bad combination of Kconfigs is used together. Later patches can clean up the Kconfigs to better wrap that dependency if the affected boards are still of enough interest to be worth that effort. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I614a1b05881aa7c1539a7f7f296855ff708db56c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-27mb/google/skyrim/var/winterhold: Add support for K3KL6L60GM-MGCTRex Chou
Update Samsung 4G K3KL6L60GM-MGCT support BRANCH=None BUG=b:243337816 TEST=emerge-skyrim coreboot Change-Id: I89b9798c16635a32dff12f1c0b65737d3c16cd59 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-27util/ifdtool/ifdtool.c: Fix default FMAP generationMaximilian Brune
According to SPI programming guide, a region limit of 0 as well as region base of 7FFFh indicates an unused/reserved region. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I790d7f5631ecef3043b2c17c41430dc4fd854f72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-27mb/google/rex: Add USB4 ANX7452 Rev 2 to USB_DB FW_CONFIGSubrata Banik
This patch adds new USB_DB FW_CONFIG to enable support for USB4 ANX7452 Rev 2. BUG=b:279647370 TEST=Able to build and boot google/rex with Proto 2 SKU Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-27mb/google/skyrim/var/winterhold: adjust the eDP panel power sequenceChris Wang
Set edp_panel_t9_ms to 8ms which means it will delay 8ms between backlight off and vary backlight off. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was passed to system integrated table; Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27soc/amd/mendocino: update FSP parameters for eDP power sequence adjustmentChris Wang
Add UPD parameter for eDP power sequence adjustment. The edp_panel_t9_ms parameter is set for bloff to varybloff. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was pass to system integrated table. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vauleChris Wang
Add UPD edp_panel_t9_ms for eDP panel sequence adjustment. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_msChris Wang
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] defineFelix Held
Instead of having multiple instances of the same magic numbers in the code, introduce and use the PCI_IO_CONFIG_INDEX and PCI_IO_CONFIG_DATA definitions. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If6f6f058180cf36cae7921ce3c7aaf1a0c75c7b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27configs/builder: add default config for Intel Archer City CRBChristian Walter
which is based on Intel Sapphire Rapids Scalable Processor chipset which was product launched on Jan. 10 2023. The site-local/* files are Intel binaries that are not published yet but coreboot build validation system would skip these binaries when they are in "site-local" directory. Please make sure you have the correct Intel binaries for your AC CRB and place them to the right location accordingly. CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage" is LinuxBoot payload, there are several ways to build it, one way is to build it from the x86_64 qemu example from osf-builder: git clone https://github.com/linuxboot/osf-builder cd examples/qemu; make kernel commit ae90fc0bb (soc/intel/xeon_sp/spr: Default to X2APIC support) would enable DEFAULT_X2APIC_RUNTIME, your LinuxBoot kernel needs to enable X2APIC support, otherwise need to set CONFIG_XAPIC_ONLY=y in your defconfig. Change-Id: I15aefc3edb2d22fc00d854850e948fe2048a992e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71969 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27mb/google/nissa/var/yavilla: Add elan touchscreen supportTony Huang
Update devicetree to support ELAN I2C generic touchscreen. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I2779c2930d89ff42233f9b20bd8abdf6dc00c0e0 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74776 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-27drivers/intel/fsp2_0: Inject newline after printing EFI GUIDSubrata Banik
TEST=fsp_print_guid() output doesn't get cobbled with other serial output and now separated by a newline character. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d47dbc5d493f86f14a1bbcf9cb5c16c0e12b841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74781 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27mb/google/corsola: Report SKU and panel ID for unprovisioned devicesRuihai Zhou
The MIPI panels will be used on the detachable variant starmie, and there will be different MIPI panels used on starmie. In order to make the different panels functional on unprovisioned devices, it needs to pass the SKU ID and panel ID to the payload to load the matched device tree for kernel. From the schematic, the starmie variant will read the LCM ID from ADC channel 5. BRANCH=corsola BUG=b:275470328 TEST=boot starmie and see FW screen display Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I6339dc3c177fb8982f77fb3bd32dc00da735fce4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2023-04-27ACPI: Make FADT entries for SMI architecturalKyösti Mälkki
Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-27soc/amd: Drop acpi_fill_madt_irqoverride()Kyösti Mälkki
It is unused. The use of field irq is problematic as it should appear relative to IOAPIC GSI bases in the devicetree. Change-Id: I460fd5fde3a7fba5518ccfc153a266d097a95a39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-27mb/google/brya/variants/hades: Correct and swap NV33 signalsTarun Tuli
The signals for the NV33 regulator were swapped (enable and power good). Switch these back to the way they should be: GPIO_NV33_PWR_EN GPP_E1 GPIO_NV33_PG GPP_E2 BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ic2a53103e1feadd7ecebd4bed02dcc34410b8e3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-27util/cbmem: Add REG_NEWLINE flag to fix matching patternKonrad Adamczyk
Match-any-character operators (eg. ".*") shall not match newline characters for BANNER_REGEX, since given regular expression matches newline explicitly. Add REG_NEWLINE flag to `regcomp` call. BUG=b:278718871 TEST=Boot firmware on skyrim, reboot. Run `cbmem -2`. `cbmem -2` returns second-to-last boot log. Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-04-26mb/amd/mayan: Update DXIO descriptors per schematicsAnand Vaikar
Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-26mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq insteadEricKY Cheng
Because WD SSD drive isn't holding the clock low for some reason. So we change to read eMMC clkreq signal instead. BRANCH=none BUG=b:274377518 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-26intel/mtl: Add get_cse_ver_from_cbfs functionAshish Kumar Mishra
This patch implements helper function get_cse_ver_from_cbfs() to retrieve the CSE Lite version from CBFE RW's metadata and calls the helper function from cse_check_update_status() TEST=Verified CSE Lite version in coreboot boot log Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74755 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-04-26mb/google/skyrim: Disable unused SPI ROM typesMartin Roth
By default, coreboot includes support for all the different types of SPI ROMs. Excluding the unused ROM types shrinks ramstage by almost 4k. BUG=b:267735039 TEST=Build & Boot ROM BRANCH=Skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72769 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-04-26soc/amd/common/block/gfx: Re-add signature check for vbios cacheMatt DeVillier
Commit c7b8809f155a ("soc/amd/common/block/gfx: Use TPM-stored hash for vbios cache validation") replaced checking the vbios signature (first two bytes) with checking against a TPM-stored hash, but there exists an edge case where the empty cache can be hashed and therefore never updated with the correct vbios data. To mitigate this, re-add the signature check to ensure that an empty cache will never be hashed to TPM. BUG=b:255812886 BRANCH=skyrim TEST=build/boot skyrim w/selective GOP enabled, flash full firmware image, ensure GOP driver is run until cache updated with valid data and hashed to TPM. Change-Id: Id06a8cfaa44d346fb2eece53dcf74ee46f4a5352 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-26sb/intel/sleepstates.asl: Use variable to enable sleepstatesArthur Heymans
In order to make supported sleep states a runtime configuration option use a variable. A follow-up patch will implement updating this variable based on an SSDT generated IntObj. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6910c2c75e668e6f75a6f431813edeb59d52dd93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-26soc/intel: Don't report _S1 state when unsupportedArthur Heymans
Since skylake Intel hardware does not support this sleep state. Trying to enter S1 by having the OS enter sleep results in a system hang on at least Alder lake (prodrive/atlas). CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices support 'skylake style' PMC PCI device for ACPI registers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/74760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-26mb/google/brya/var/taeko: remove rtd3 for emmcJoey Peng
Remove rtd3 for emmc device on taeko BUG=b:271003060 TEST= emerge-brya coreboot, flash to DUT and can boot to OS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-26mb/google/brya/var/taniks: remove rtd3 for emmcJoey Peng
Remove rtd3 for emmc device on taniks BUG=b:271003060 TEST=emerge-brya coreboot, flash to DUT and can boot to OS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-26mb/google/myst: Enable tis_plat_irq_statusJon Murphy
This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:277297687 TEST=builds Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74286 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-26mb/google/myst: Configure WLANJon Murphy
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mapping derived from myst schematic. BUG=b:275965982 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-26mb/google/myst: Enable PCIe devices in devicetreeJon Murphy
Ensure that DXIO descriptors are updated using info from AMD and Myst board schematics. BUG=b:275960920,b:276744321 TEST=builds Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74112 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-26mb/siemens/mc_ehl4: Enable SD cardMario Scheithauer
This mainboard has SD slot available and therefore it should be enabled. Use the same SD card configuration as for mc_ehl2 mainboard. Change-Id: Icd9b25301311679cf93b05ba83a24e551261a020 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-26mb/siemens/mc_ehl4: Switch RTC type and connectionMario Scheithauer
This mainboard has the RTC RV-3028-C7 connected to the I2C1. TEST: - Console Log shows no errors for RV-3028-C7 during I2C1 init - Finalize device for I2C 00:52 shows correct date and time Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74652 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-26mb/siemens/mc_ehl4: Adjust USB settingsMario Scheithauer
Correct the USB settings, suitable for this mainboard. Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74651 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-26mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codesMario Scheithauer
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to '0'. On this mainboard NC FPGA is connected to PCIe root port #1 (00:1c.0). Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-26mb/siemens/mc_ehl4: Adjust GPIOsMario Scheithauer
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the GPIOs must be adjust according to the circuit diagram for this mainboard. Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-26mb/google/brya/var/omnigul: Disable Tccold HandshakeDtrain Hsu
The patch disables Tccold Handshake to prevent possible display flicker issue for Omnigul board. Please refer to Intel doc#723158 for more information. BUG=b:279539826 BRANCH=firmware-brya-14505.B TEST=Verify the build for Omnigul board Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74737 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-26mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iae2dc0a934f0ea3ca59d8a811f1daeedb090a7bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-04-26soc/amd/phoenix/Kconfig: Update commentFred Reitberger
Fix copy-paste comment on closing endif Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9671a9228c304988eb3903391f74a21d80d0a8bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-26AMD binaryPI: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
Change-Id: I799f61d13f7ae3ea753869ded282c14ed566793a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/intel/common: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
For the first IOAPIC, use the common MADT generator with default IRQ overrides. Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/amd: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: I2de941071fca6f7208646a065a271fbf47ac2696 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74354 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26asus/p2b, emulation/qemu-i440fx: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
For uni-processor platforms, with SMP=n or MAX_CPUS=1, neither the LAPIC or IOAPIC MADT entries are added. Change-Id: I8777f4e3b37fe7b564189c6bf48e3988026b2361 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26aopen/dxplplusu: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
IRQ override from IRQ #0 to GSI #2 is changed from MP_BUS_EISA to MP_BUS_ISA. Change-Id: I115df037fd79e120b04e6aff9e53f963f045b997 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/intel/baytrail,braswell: Use COMMON_MADT_IOAPICKyösti Mälkki
Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: I3a61a0ceb0e6e4a09570beef6d0170354eb498ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26sb/intel: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
i82801gx, i82801ix, i82801jx: Maintain IRQ #0 to GSI #2 override as positive edge trigger. ibexpeak, emulation/qemu-q35: Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: Ia8a04daf3a79d9f2f4801dc85e4975278e30dc8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADTKyösti Mälkki
Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms' implementations of adding IOAPIC and IRQ override entries for ACPI MADT tables. Platforms that have a more complex MADT may continue to add custom entries using CUSTOM_ACPI_MADT. Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26arch/x86/ioapic: Promote ioapic_get_sci_pin()Kyösti Mälkki
Platform needs to implement this to provide information about SCI IRQ pin and polarity, to be used for filling in ACPI FADT and MADT entries. Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/intel: Introduce ioapic_get_sci_pin()Kyösti Mälkki
According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26ACPI: Add acpigen_write_PTC()Kyösti Mälkki
Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26cpu/intel/speedstep: Separate single SSDT CPU entryKyösti Mälkki
Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26acpi/acpi.c: Reduce scope of some functionsArthur Heymans
These functions are only used in one compilation unit. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74756 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-25Documentation/mainboard/hp: Add more about internal flashingVesek
Add a more detailed explanation of internal flashing on the HP Compaq 8200 Elite SFF. Signed-off-by: Václav Straka <venda.straka@gmail.com> Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-04-25util/docker/jenkins-node: Drop Zephyr SDKFelix Singer
The version of the Zephyr SDK that is used is quite old and Zephyr hasn't been really used. Thus, drop it and also its dependencies from u-boot. Change-Id: Ie498d687e1566133adf650166117d8f68fcfdaf6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-04-25util/docker/jenkins-node: Allow pip to install packages system-wideFelix Singer
Call pip3 with `--break-system-packages` allowing it to install packages system-wide. This fixes building the Docker container. Change-Id: Id093f2c69fec43556c434fbca7b36095a7e6bd97 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-25util/docker/jenkins-node: Merge package installations into first stepFelix Singer
It's not necessary to have multiple steps for installing packages and requirements. Just merge the two install steps to one. Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74245 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-25mb/google/nissa/var/yaviks: Update devicetree for UFC usb portTony Huang
USB port 6 connects to a USB front camera, it should always probe. Remove probe by rear camera fw_config. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I554046718f6e0eb7197970f9a3808b3e1ea7f99c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-25mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIGTony Huang
Update devicetree -Enable USB2 port5 for WWAN -Update OVTI8856 setting -Update USB2/3 Type-A 0/1 port location Probe devicetree based on FW_CONFIG -pen garage -rear mipi cam -USB WWAN BUG=b:273791621, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-25Documentation/releases/coreboot-4.20: Add toolchain updates sectionElyes Haouas
Change-Id: I5fff8b97f6b85165a71aa2a86417f27986fd25fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-04-24mb/google/myst: Set system type to laptopJon Murphy
BUG=b:277294070 TEST=None Change-Id: I0aa4e0bcfb06e5e5cb7e9d52f2d82b5818925267 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74284 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24mb/google/myst: Store XHCI PCI resourcesJon Murphy
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. BUG=b:277273428 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I608d51f438681ac529323c23cc707845a3d609d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74281 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24mb/google/myst: Enable gfx_hdaJon Murphy
Enable gfx_hda to allow for audio over hdmi. BUG=b:277219546 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I58096f1408f66f968af1494e487cf2bfc43b9a0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74278 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24mb/google/myst: Enable crypto in devicetreeJon Murphy
Add the crypto device to the devicetree. BUG=b:277214359 TEST=builds Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74275 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24asus/p2b: Remove MADT LAPICKyösti Mälkki
Fix after 'commit 69a13964ea6c ("sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC")' broke interrupt delivery in kernel. Apparently combination of LAPIC without IOAPIC is too rare to be well supported. Change-Id: I5e2fbf358cf644665b897afb0a9404abb5ca1df2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74472 Reviewed-by: Branden Waldner <scruffy99@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-24soc/mediatek/mt8183: Fix set but unused variableArthur Heymans
This fixes a clang warning. Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-24vendorcode/mediatek/mt8192: Add or remove bracketsArthur Heymans
This fixes clang compilation warnings about logic problems and superfluous brackets. Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-24soc/mediatek/dptx.c: Remove set but unused variablesArthur Heymans
This fixes clang warning about set but unused variables. Change-Id: I3a3345e33380862d6939b61485f6d1eefa3d1815 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74547 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2023-04-23include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gbFelix Held
Add the missing 'b' to the 4gb so that get_top_of_mem_above_4gb is in line with get_top_of_mem_below_4gb. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/amd/glinda: drop code for non-existing eMMC controllerFelix Held
Glinda doesn't have an eMMC controller and also doesn't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Glinda. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49ead01075780ea97dae99a36632f7659fd00587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74662 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-22soc/amd/phoenix: drop defines for non-existing eMMC controllerFelix Held
Phoenix doesn't have an eMMC controller, so remove the remaining eMMC- related defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I412c968479d23deb7f2e060b26b4a56ec9c764f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/amd/mendocino: drop code for non-existing eMMC controllerFelix Held
Mendocino and Rembrandt don't have an eMMC controller and also don't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22mb/google/octopus: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:268342532 BRANCH=firmware-octopus-11297.B TEST=Observe kernel ec panic handler run when ec panics Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I37e566e459f39f8bc2dafc3c3915260259730ca6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22mb/google/dedede/var/boxy: Generate SPD ID for supported memory partkevin3.yang
Add boxy supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 3. Micron MT53E512M32D1NP-046 WT:B BUG=b:278983561 TEST=Use part_id_gen to generate related settings Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I317f2b31774627706babdea10776af05ab692d1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-22mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviksTony Huang
Yavilla board memory id setting references to yaviks. This CL aligen it with yaviks. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56AK6BX069 2 (0010) K3LKBKB0BM-MGCP 2 (0010) H58G56BK7BX068 3 (0011) MT62F1G32D2DS-026 WT:B 3 (0011) K3KL8L80CM-MGCT 3 (0011) H58G66BK7BX067 4 (0100) MT62F2G32D4DS-026 WT:B 4 (0100) K3KL9L90CM-MGCT 4 (0100) H58G66AK6BX070 5 (0101) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22mb/google/brya/variants/hades: Swap LAN and SD Card PCIE PortsTarun Tuli
To aid in layout, the PCI ports for LAN and SD card were swapped. SD Card is now on RP3 (clksrc 4) LAN is now on RP8 (clksrc 3) BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22soc/intel/meteoerlake: set power limits dynamicallySumeet R Pawnikar
Set power limit values dynamically based on Meteor Lake CPU TDP and PCI ID of SKU. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values for 15W SKU on Rex board Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gatingFrank Chu
The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue. Please refer Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Verify the build for marasov board Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74627 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-22mb/google/corsola: Rename common config from `STARMIE` to `STARYU`Ruihai Zhou
The STARYU is the mt8186 detachable reference design, and the STARMIE is a variant of STARYU. Let's rename the common config from STARMIE to STARYU, and we can select the STARYU config for the follow up mt8186 detachable variant. BRANCH=corsola BUG=b:275470328 TEST=./utils/abuild/abuild -t google/corsola -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: If75e94e86420b0a216fe7a1a9dee9cb42bbd985c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74654 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-04-22samsung/lumpy: Use APMC definesKyösti Mälkki
Change-Id: I658596da1d84b486126d751b6066c3efd3f65290 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-22lib/version: Move board identification stringsKyösti Mälkki
These strings are now only expanded in lib/identity.c. This improves ccache hit rates slightly, as one built object file lib/version.o is used for all variants of a board. Also one built object file lib/identity.o can become a ccache hit for successive builds of a variant, while the commit hash changes. Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-22soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFNFelix Held
Since it's an internal bus, it's PCIE_ABC_C_DEVFN and not PCIE_GPP_C_DEVFN. This also makes it consistent with the rest of the internal PCI buses. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63Felix Held
In the PPRs #57019 Rev 3.03 and #57396 Rev 3.04, SMITYPE_XHC3_PME, SMITYPE_XHC4_PME and SMITYPE_CUR_TEMP_STATUS_5 are defined, so add those defines. When doing the initial update for Phoenix, at least XHC3 and XHC4 PME events were missing from the PPR. Those two are the PME events of the two USB4 controllers. SMITYPE_XHC2_PME doesn't exist on this SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6fff9175b73cc9d0fd324d4a568a5761b92d078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 03:58:43 +0000