diff options
author | Joey Peng <joey.peng@lcfc.corp-partner.google.com> | 2023-03-27 09:30:17 +0800 |
---|---|---|
committer | Nick Vaccaro <nvaccaro@google.com> | 2023-04-26 15:14:18 +0000 |
commit | f63c7222be7518e3450008c69274e959f1972f8c (patch) | |
tree | cb60d0aa502af42e29f2cfca80c42cf405064f31 | |
parent | fd7f51546e26828022dedcd877b8190d18f387bb (diff) |
mb/google/brya/var/taniks: remove rtd3 for emmc
Remove rtd3 for emmc device on taniks
BUG=b:271003060
TEST=emerge-brya coreboot, flash to DUT and can boot to OS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
-rw-r--r-- | src/mainboard/google/brya/variants/taniks/overridetree.cb | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index acacec34fe..01baf40ad4 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -350,21 +350,12 @@ chip soc/intel/alderlake end end device ref pcie_rp9 on - # Enable NVMe PCIE 9 using clk 0 + # Enable PCIE 9 using clk 0 for eMMC register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" - register "srcclk_pin" = "0" - register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" - device generic 0 on - probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED - end - end probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED end device ref pch_espi on |