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This patch adds TCSS XHCI device ID for ADL-N CPU which is required
for USB3 port enumeration.
Document Reference: 645548 revision 1.0 (Chapter 2.3)
BUG=None
BRANCH=None
TEST=Check if device is detected correctly and ACPI entries are
generated for device 0d.0
Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Windows 11 installer expects the TPM to reside under \\_SB_.PCI0 in
ACPI device hierarchy, otherwise the TPM is not detected. Hardcode
the path to fix the issue.
TEST=Boot Windows 11 on Clevo NV41MZ and see the TPM is detected
correctly
TEST=Boot Ubuntu 20.04 on Clevo NV41MZ and see the TPM is detected
correctly
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.We checked power on sequence requires enable pin prior to reset pin, added delay to meet the sequence and test passed on various eMMC SKUs.Base on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.
BUG=b:224648680
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 2500 cycles passed on primus
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Originally, dram size is hard-coded to 4GB by default. To support
different dram size, calculate it from the mem chip info stored
in CBMEM.
BUG=b:206014043
TEST=Output "dram size: 0x100000000" on Kingler
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Store dram info in cbmem for ramstage or payloads to use.
BUG=b:206014043
TEST=Build pass on Kingler
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Update iPXE stable from commit id ebf2eaf515:
Mar 18 10:24:08 2019 +0000
[intel] Add PCI ID for I219-V and -LM 6 to 9
to commit id 6ba671acd9:
Jan 17 16:17:17 2022 +0000
[efi] Attempt to fetch autoexec script via TFTP
This brings in 424 new commits and fixes the build with coreboot-sdk
2021-09-23_b0d87f753c.
TEST=Build PC Engines apu2 board and boot it over network with the
iPXE
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ide12a3a3082f9ea027e180518a80e6c0772b1232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Prevents bad things from happening later when these new nodes are used.
This issue is hard to observe because:
1. Heap is zero-initialized, so you need to use allocated memory
filling it with non-zero values, free, allocate it again, use
uninitialized.
2. Most of allocated memory is not freed.
3. Implementation of free() does something only for one last malloc'ed
block, making most of freed memory unavailable for future
allocation.
Change-Id: I38a7ec1949d80f7a2564fac380ce94de6056a0c7
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62928
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 5a0ad1186 missed one chip config member that got converted to
snake case in commit 215a97ee1.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie92106f0fee0bb18863b7063c07673e0f7995c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63005
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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cr50_get_board_cfg() may be called in ramstage for some mainboards in
order to determine the BOARD_CFG register's value. The code was
written assuming that the firmware version was already retrieved, but
for boards calling this in ramstage, this is not the case. Therefore,
instead of using the cached cr50_firmware_version (which is all 0s in
ramstage at that time), use the cr50_get_firmware_version function
instead.
BUG=b:225206079, b:220685274
BRANCH=firmware-brya-14505.B
TEST=boot on brya0 and see:
[INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94
[INFO ] Enabling GPIO PM b/c CR50 has long IRQ pulse support
in the logs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf
BUG=b:220814038
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf
BUG=b:219891328
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.
TEST=On Mandolin both IOAPICs are still correctly detected by Linux.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently memory parts that use the same SPD are assigned the same ID by
spd_tools. This commit adds support for exclusive IDs. When given an
exclusive ID a memory part will not share its ID with other parts unless
they also have the same exclusive ID.
BUG=b:225161910
TEST=Ran part_id_gen and checked that exclusive IDs work correctly and
that the current behavior still works in their abscence.
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Kinox is designed to 8-layer PCB. In order to reduce the length of
memory singals, the DDR4 is designed from interleaved to
non-interleaved.
BUG=b:210094309
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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GL9763e doesn’t support L0s state, so disable L0s at the root port.
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
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This change provides config for devicetree to control ASPM per port
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles on taeko.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The workaround causes the eMMC controller to not enter its L1
during the boot process
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
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Add an option to set L1 entry delay to Max for GL9763E. The L1 entry
delay will be changed to expected value by sdhci-pci-gli driver in
Linux v5.14.
BUG=b:220079865
TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is
0x3FF.
Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Martin L Roth <martinroth@google.com>
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Add missing CONFIG_ to the Boot Timeout parameter.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I88f4aa0286a77f6c94b5e5ec97a0034ea7594b4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62920
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The cpu device listed in MediaTek platforms' devicetree.cb doesn't
actually do anything, except causing an error during device
initialization:
CPU: 00 missing read_resources
Therefore, remove it from the devicetree.
BUG=b:224419346
TEST=emerge-corsola coreboot
TEST=Krabby booted up successfully
BRANCH=none
Change-Id: Ibf9f7cf65da6a0dd0a0e1f556d5772573ba3e930
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62805
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"Total time" calculation changed after CL 59555 to include
"1st timestamp" value in the calculation. This patch restores original
Total Time calculation where "1st timetamp" is subtracted from
"jumping to kernel". If pre CPU reset timestamps are added (negative
timestamps), "Total time" calculation still includes the pre-reset time
as expected.
1) Before https://review.coreboot.org/c/coreboot/+/59555:
0:1st timestamp 225,897
1101:jumping to kernel 1,238,218 (16,316)
Total Time: 1,012,281
2) After https://review.coreboot.org/c/coreboot/+/59555:
0:1st timestamp 225,897
1101:jumping to kernel 1,238,218 (16,316)
Total Time: 1,238,178
3) After this patch:
0:1st timestamp 225,897 (0)
1101:jumping to kernel 1,238,218 (16,316)
Total Time: 1,012,281
BUG=none
TEST=Boot to OS, check cbmem -t on Redrix board
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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The APCB files that provide the firmware components running on the PSP
some mainboard-specific information like the DRAM interface
configuration. Those files aren't yet in the upstream 3rdparty/blobs
repository, so only add those files if they are present and print that
no APCB was added and the image won't boot if they aren't present.
TEST=Both cases behave as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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To have enough space in the A/B RW sections, increase those sizes to 4
MByte and decrease the RO section size to 6 MByte to free up the space
needed for that.
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Since CB:62741, the EC values are backed up to the CMOS when entering
S3, S4 and S5. Consequently, they don't need to be stored when they're
changed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If0ea392afae4a4d3c605cdea3c5896fbff606215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The EC values will be changed when entering S3, S4 or S5, so move
the function that stores the current settings outside of logic
that restricts it to S4 or S5. This means the state isn't lost
when entering S3.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia007a8ad9c08a309489e9f64f1ed311858bfcd10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character
is got or access violation happens.
Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Add WiFi SAR table
BUG=b:225285426
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8fa833409bd69e080fda735c89015b9548252190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB
sideband access and exposes API for TCSS usage.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:211672259
BRANCH=firmware-zork-13434.B
TEST=ALC5682I-VS audio codec can work
Change-Id: Icd4321ec0a284e35511dd4b860a16506f54cf663
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:215292608
BRANCH=firmware-zork-13434.B
TEST=ALC5682I-VS audio codec can work
Change-Id: I0b0231a3ee9c0dad289ffd50607b3ae6201f56a0
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are
add to overridetree.cb where WWAN is present for vell.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig which
updates PMC settings in the IFD for Alder Lake A0 silicon.
As Alder Lake A0 is intermediate stepping, and the IFD is locked in the
production systems, so the Kconfig is deselected.
BUG=b:190588098
BRANCH=firmware-brya-14505.B
TEST=Build the coreboot for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Although the panel initializes fine and the fw recovery screen is
displayed without issues, the current power-on sequence of the
PS8640 violates the spec of the PS8640, which can be confirmed by
measuring it with an oscilloscope.
The sequence is:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#
This flow will increase 110ms if firmware display is enabled in
krabby. For normal booting flow, the firmware will not be enabled,
so it will meet boot time requirements of Chrome OS. (Less than 1s.)
Datasheet name: PS8640_DS_V1.4_20200210.docx.
Chapter: 14.
BUG=b:222650141
TEST=show fw display normally in krabby.
TEST=result of waveform meets the spec.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, PSPP will be reenabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
|
|
Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, the PSPP policy will be switched to balanced again.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This patch creates a new helper function to enable P2SB BAR.
`p2sb_dev_enable_bar()` takes the PCI P2SB device address (B/D/F)
and BAR address (combining high and low base addresses).
BUG=b:224325352
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
|
|
The touchscreen slave address for landrid is 0x10 same as lantis, so we use SSFC to switch touchscreen controller.
BUG=b:222976965
TEST=emerge-dedede coreboot
Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Use GEN3 from enum dxio_link_speed_cap instead of the number 3.
TEST=Timeless build results in identical firmware image for guybrush
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
Change request here:https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
BUG=b:200113959
TEST=Verified on Meteor Lake platform, without any compilation error
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1f33db43f7932cf6d165d0c70a0e2922dad00a09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Commit 215a97ee1c4cd87b266d63e32bf0b379e18fe849 (soc/intel/adl/chip.h:
Convert all camel case variables to snake case) converted the camel case
used in the parameter name to snake case, but
commit bd529e2e200a8fbfd455dd62be0494a2b727b9a5 (mb/google/nissa/var/
nivviks: Add TcssAuxori for nivviks) still used the old names which
breaks the upstream build. his patch is intended to be merged via
fast-path before the 24h are over to fix the tree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b9049553889c77bd8c59a2c4564d36d836a4eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62927
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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In MT8186, we need to disable spm_thermal to prevent it from
influencing other wdt status.
There are two hardware pathes which are used for asserting watchdog
from thermal. We can disable status of path 1 because status of
path 2 is used.
1. Thermal -> SPM -> WDT
2. Thermal -> WDT
Spm_thermal (path 1) is a flexible option for software control, and
the hardware designer suggests that we should disable it if we don't
use it.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0ffde6bad3000a64e3b5782edaa72c62da034302
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62890
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Because we close external signal in kernel driver since MT8195, it's
more reasonable to trigger sw reset with exteranl signal again
whenever the wdt status is not equal to 0.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62797
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable SBU orientation handling by SoC for both USBC port0 and USBC
port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver,
but that do not flip the data lines. Hence we need to set bits for both
the USBC ports.
BRANCH:None
TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on
nivviks board and verified USBC display is working on both the ports in
normal and inverted connections.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Without setting the set_resources field for soc_ops, we will get an
error during device initialization:
[ERROR] CPU_CLUSTER: 0 missing set_resources
Because the set_resources field is considered mandatory, explicitly set
it as no-op noop_set_resources.
BUG=b:224419346
TEST=emerge-corsola coreboot
TEST=Did not see the error on krabby
BRANCH=none
Change-Id: Ic82b86f0482a9de09e942c1674be5f0ac615851f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Based on the latest schematic, replace amp max98357 with max98360.
BUG=b:224692387, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62887
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add wifi sar for galnat/galnat360
Use SKU ID to load wifi table.
Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
galnat (sku id:0x140000)*
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
galnat360 (sku id:0x2B0000)*
BUG=b:222008376
TEST=emerge-dedede coreboot chromeos-bootimage \
coreboot-private-files-baseboard-dedede
verify the SAR table is correct in each project
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I868a7416a002732736cabea48ce80548ea75e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
struct mem_chip_info {
...
struct { --> If no struct name, can't access the channel structure
...
} channel[0];
};
BUG=b:182963902,b:177917361
TEST=Build pass on Kingler
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I8dcd3b52f33f80afb7885ffdcad826d86b54b543
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Volmar does not support Thunderbolt, therefore disable all of the TBT
devices in the devicetree. The volmar fit image had been disabled already, cf. chrome-internal:4459289.
BUG=b:2233193
TEST=Build and run on DUT.
Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Configure GPIOs according to updated schematics.
- GPP_A21 from NC to TCP_DP1_CTRLCLK.
- GPP_A22 from NC to TCP_DP1_CTRLDATA.
- GPP_E22 from DDIA_DP_CTRLCLK to NC.
- GPP_E23 from DDIA_DP_CTRLDATA to NC.
BUG=b:214025396
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This sets EPP value to be 45% for all Adl RVP variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
1.Change I2S GPP_Sx (S0-S3) Native PAD Configuration from NF2 to NF4
2.Select CS35l53 AMP driver for Vell variant.
Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c
Signed-off-by: Shon.Wang <shon.wang@quanta.corp-partner.google.com>
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This patch is adding support for Cirrus Logic CS35l41/CS35l53
smart amplifier. This part is now used in number of new chromebook's
HW designs by several vendors.
This driver uses the ACPI Device Property interface to generate
the required parameters into the _DSD table format expected by
the kernel. For detailed information about these properties, please
check Linux kernel documentation:
/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml
Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:224618411
TEST=util/abuild/abuild -t GOOGLE_SKYRIM with and without APCB
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Needed so i2c communication works.
BUG=b:224618411
TEST=build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8ec7c18cae509b5683cb73153fd6d3747cf9d753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62874
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This will fix:
> [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50!
BUG=b:224618411
TEST=Compile skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5add694506ad089adcc8961f101bf507bc39a522
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62873
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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serially""
This reverts a change that was causing hangs and exceptions during boot
on an ADL brya4es.
The hang (or APIC exception) occurs at what appears to be the FSP MP
initialization sequence, prior to the "Display FSP Version Info HOB"
log being displayed :
[DEBUG] Detected 10 core, 12 thread CPU.
[DEBUG] Display FSP Version Info HOB
This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924.
BUG=b:224873032
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es
is able to successfully reboot 200 times without any issues.
Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This message is not really an error message, so BIOS_ERR is
inappropriate. The message does seem more like a warning though,
that the developer could have multiple Kconfigs selected to send EOP,
therefore switch to BIOS_WARN instead.
BRANCH=firmware-brya-14505.B
TEST=build
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I57a34334007a6a7443302c2f25de3d5c87c85573
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Change-Id: I22e4a7c6385ffb9ba77e10edad41ef3d027ba694
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62906
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ibf91a879478e03b584756dc24fe33fb013803f9d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
TCSS ASL code was carried forward from TGL and it used to follow the same
sequence.
Recently as part of s0ix hang issue, it was found that sending IOM
MCTP command as part of TCSS D3 Cold enter-exit sequence created an
issue.
We discovered that due to change in hardware sequence, ADL should not
set/reset IOM MCTP during D3 cold entry or exit. This patch removes the
bit setting from ASL file to prevent hang in the system.
This patch also removes obsolete Pcode mailbox communication which is
no longer required for ADL.
BUG=b:220796339
BRANCH=firmware-brya-14505.B
TEST=Check if hang issue is resolved with the CL and no other regression
observed
Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62861
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The coreboot toolchain is a huge blob and increases the size of the
build a lot. If needed, the specific toolchain can be added before
building the ISO or with `nix-shell` later in the live system, as shown
below.
$ nix-shell -p coreboot-toolchain.i386
Thus, remove this from the todo list.
Change-Id: Ia24ceb84f202828f1c97d3ba5bafbf6af0361bdb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Use C code to generate MS0X entry and provide variant hook.
BUG=b:207144468
TEST=check SSDT table has the same entry.
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x148)
}
Else
{
\_SB.PCI0.STXS (0x148)
}
}
}
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This was to merge PCIe ACPI code to WWAN device. But, now use recent
_DSD generation changes in FM driver instead. PCie generic driver is
not used for WWAN at this time.
Also, RTD3 devices are moved to overridetree.cb where WWAN is
present.
BUG=b:221250331
BRANCH=firmware-brya-14505.B
TEST=
Check that _DSD is added to WWAN device in SSDT for the variants.
Check that RTD3 is added to WWAN device in SSDT for the variants.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Follow thermal team design to update thermal table.
BUG=b:223492897
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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For galnat platform, support 2nd ELAN touchscreen via SSFC.
Define FW_CONFIG bits 39 - 40 (SSFC bits 7-8)
for touchscreen controller switch.
BUG=b:221002826
TEST=touch screen is functional.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id3501205b147c9dc3c96ce8381a3e7492ae8258e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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In the devicetree case where a generic device underneath the Intel PCI
CNVi device carries the device properties, the incorrect device was
passed to wifi_ssdt_write_properties.
Also while here, update the UUID for `DmaProperty` to match what
Microsoft defined here:
https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports
BUG=b:215424986, b:220639445
TEST=dump SSDT and see that _PRW for CNVi device is no longer garbage,
but contains the value from the devicetree (GPE0_PME_B0).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
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In usb4_retimer_fill_ssdt(), it search all dpf ports and shows message
in not support dpf ports.
It's not error and changes the loglevel prefix to BIOS_INFO.
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I508ec7662e078893f944edb3d68364c57d5c5a73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to
BIOS_INFO instead.
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I9dc852a0cd30f95506c205f161a05e8a8c44fcd5
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
In most boards, it doesn't write OEM_NAME in CBI to override the
manufacturer name in the SMBIOS table. It' better use the "BIOS_INFO" than "BIOS_ERR"
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I52eb1e6926eaac30b1dbee13ab750ef15b466d89
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Modify 15W SOC default power settings for kinox.
- PL2 39W
- PL4 100W
- Psys_PL2 65W
- Psys_imax_ma 5000ma
- bj_volts_mv 20000mv
BUG=b:213417026, b:222599762
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62627
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch refactors the current P2SB common code driver to accommodate
the future SoC platform with provision of more than one P2SB IP in
disaggregated die architecture.
IA SoC has only one P2SB in PCH die between SKL to ADL. Starting with
MTL, one more P2SB IP resides in IOE die along with SoC die. (PCH die is
renamed as SoC in MTL.)
P2SB library (p2sblib.c) is common between PCH/SoC and IOE, and p2sb.c
is added only for PCH/SoC P2SB.
BUG=b:224325352
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
1.Assert eMMC enable pin in bootblock
2.Deassert eMMC reset pin in bootblock
BUG=b:220821454
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This change supports the configuration and enablement of
mdp clock to vote for turbo and supports different display
panel resolutions and framerates.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ibf4f11d02b0edf83461dbb7af99fda5f33cd5b71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62371
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add support for EDP (Embedded DisplayPort) clocks in coreboot.
This change supports the configuration and enablement of
EDP PIXEL, LINK, LINK_INTF and AUX clocks.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Follow the latest schematic change, gpio will match the baseboard.
Return the current table as override.
BUG=b:223677877
TEST=audio is functional on board_0.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Currently, many Linux drivers use DMI quirks to identify ChromeOS
devices and handle them accordingly: namely they look for the SMBIOS
system manufactuer to be "GOOGLE" or "Google", and the bios-vendor to be
coreboot. Historically this was consistently the case, but recent model
ChromeOS devices allow the OEM to set the mainboard manufacturer, which
is also the default system manufacturer. This breaks many DMI quirks,
notably ones used by SOF (sound open firmware) for audio.
To fix this, set the system manufactuer for ChromeOS devices to "Google"
for devices selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID, leaving the OEM
customization in place for the mainboard manufacturer. Since boards
selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID are the only ones overriding
the default mainboard manufacturer, they are the only ones which need
this correction.
Test: build/boot google/bloog with Linux 5.16, verify SOF drivers
correctly detect device as a Chromebook and load the appropriate
audio firmware.
Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62796
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add ADL-P MCH ID 4, 8, 9, 10 into this list.
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Cache the BIOS region and extended BIOS region if the boot device is
memory mapped, which is mostly the case with Intel SoC platform.
Having the ROM region cached helped to improve the pre-boot time.
TEST=Able to boot redrix to Chrome OS without seeing any sluggishness.
Additionally verified on EHL board (from siemens), shows significant
savings in payload loading time as below:
Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:
upstream:
90:starting to load payload 1,072,459 (1,802)
958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619)
with this patch:
90:starting to load payload 1,072,663 (2,627)
958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This patch provides a way to cache `ext_bios` region for all stages to
save boot time.
TEST=Able to see the ext_bios region in MTRR snapshot when cached on
the Brya variants.
Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:
upstream:
90:starting to load payload 1,072,459 (1,802)
958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619)
with this patch:
90:starting to load payload 1,072,663 (2,627)
958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This patch cleans up `efi_datatype.h` to allow other SoC and/or driver
code to use this file.
`PiPei.h` file only gets added from UDK2017 hence, the platform with the
older EDK2 base (prior to UDK2017) is unable to resolve this file
dependency.
This CL removed the `PiPei.h` header and only added the required header
file `PiPeiCis.h` for platforms with UDK base >= 2017.
BUG=b:200113959
TEST=Able to build Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9177814fcf41e5950ace94050356f0273f765c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
dev->ops = &wifi_cnvi_ops need is_cnvi be true. This cause the exclusive
statement so is_cnvi never be true in !DEVTREE_EARLY.
BUG=b:224317408
TEST=no assertion in coreboot.
[EMERG] ASSERTION ERROR: file 'src/acpi/acpigen_pci.c', line 24
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I1ca6312ce164c43021686b483f6579164614cede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Move selects from Kconfig.name to Kconfig so that the configuration is
in one place and not distributed over two files.
Change-Id: I500f6422c1f8975de8b0bcc8b95cba2bcd4ebe27
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Enable PCIe-eMMC bridge for Kinox.
BUG=b:218786363, b:211176722
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters.
BUG=b:221180425, b:222020226, b:221182596
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
As per ME BWG, the patch retries MEI CSE DISABLE command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.
TEST=build and boot the Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
As per ME BWG, the patch retries END_OF_POST command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.
BUG=b:200251277
TEST=Verify EOP retry mechanism for brya board.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This adds the following commits:
* a069321 cezanne: Update SMU firmware to 64.62.0
* d8a51cb cezanne: Upgrade ABL to 0x22146070
Change-Id: I066252eda56b8b62db420cbcfc95c97875a3b6d1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Remove global variable and use 'pcidev_path_on_root()' to get the base
address of PCIe controller.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Add chip config for setting PCIe config.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
The current SMM framework only allows the mainboard code to handle GPEs.
i.e., Events 0 - 23. This change allows the mainboard code to handle any
SMI events not handled by the SoC code. This will allow the mainboard
code to handle `SMITYPE_ESPI_SMI`.
BUG=b:222694093
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Rename `BOARD_HP_SNB_IVB_LAPTOPS` to `BOARD_HP_SNB_IVB_LAPTOPS_COMMON`
to indicate and to make it clear that this option serves as base for
others.
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and also with
`INCLUDE_CONFIG_FILE` disabled. coreboot.rom remains identical.
Change-Id: Icadeb8a33ae0787d2cd5da460065a2ed15256d64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and
coreboot.rom remains identical.
Change-Id: I54367c7c663ad288ccdcbd4e7289546489a68f30
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is
directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP
firmware successfully.
BUG=b:222188263, b:223906569
TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint
Firmware Test.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59193
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US,
which controls how long to wait for an I2C devices to
produce/accept all the data bytes in a single transfer.
(The device can delay transfer by stretching the clock of
the ack bit.)
The default value of this new setting is 500ms. Existing
code had timeouts anywhere from tens of milliseconds to a
full second beween various drivers. Drivers can still have
their own shorter timeouts for setup/communication with the
I2C host controller (as opposed to transactions with I2C
devices on the bus.)
In general, the timeout is not meant to be reached except in
situations where there is already serious problem with the
boot, and serves to make sure that some useful diagnostic
output is produced on the console.
Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BUG=b:224325352
TEST=Able to build ifdtool.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3564efa27d0271286435284e745458aada987008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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