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2022-11-04include/device/pci_def.h: Add some PCIe DPC/AER definitionsTim Chu
* Add DPC related definitions which are defined in 7.9.14 of PCIe 6.0 spec. * Add AER related definitions which are defined in 7.8.4 of PCIe 6.0 spec. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69106 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-11-04Revert "soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function"Felix Held
This reverts commit 3bc9fbb496c7e1ae346c8d7e98d2bcabbbbe8673. The patch that added hob_enhancedwarningloglib.h was marked as private after the Jenkins run, so I didn't see and submit it before submitting the patch that gets reverted by this commit. Temporary revert this patch to fix the coreboot tree until the issue with the missing patch is sorted out. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If56609dd2d91a70fe7e99ce86e0341f2b3fee3d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69229 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04Revert "drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling"Felix Held
This reverts commit 059902882ce56502124375c9395ebe8b49640710. A dependency of the previous patch that added the get_ewl_hob function used by this patch was missing, so this patch needs to be temporary reverted to revert the patch that breaks the build due to the missing dependency. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb2fa27e75eede1648ddbf82c8bfbeeb2e9220a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69228 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-11-04mb/prodrive/atlas: Add IBECC Kconfig optionMaximilian Brune
Add an option on Atlas to enable IBECC (In Band Error Correction Code), which is currently needed for endurance testing. Test: start atlas mainboard with Linux. See in dmesg that IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs and see in dmesg that Linux handles it. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-11-04soc/intel/alderlake: Add IBECCMaximilian Brune
Add In Band Error Correction Code to Alderlake SOC's. It's currently needed and tested for the Prodrive Atlas mainboard. After enabling it in the UPD, FSP-M takes care of enabling IBECC. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68756 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04payloads: Make PAYLOAD_NONE a bool outside of the choiceMartin Roth
Instead of having the config option PAYLOADS_NONE inside the choice of payloads, make that a separate choice that enables the payload menu. If the no_payload option is selected, this hides the other options and keeps them out of the saved config file and config.h Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I932c65630261a5b39809abf4dfbda5bf932c6684 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-11-04soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-04drivers/ocp/ewl: Add EWL driver for EWL type 3 error handlingShelly Chang
Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB and prints EWL type 3 primarily associated with MRC training failures. Change-Id: Ibd5b521bafd457505db4147c5d3fe41364a09045 Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69145 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility functionJohnny Lin
Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69144 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-04soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-MJohnny Lin
EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may contain several warnings/errors related to core, uncore and memory, etc. mainboard can override it in its romstage.c for its own Enhanced Warning Log check. Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69143 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04soc/mediatek/mt8188: Disable input-gating for big-core SRAMLiju-Clr Chen
The input-gating is an experimental feature (but unfortunately default enabled) and would lead to crash on MT8188, so we have to disable it in the firmware stage. BUG=b:233720142 TEST=CPUfreq in kernel test pass. Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69089 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driverLiju-Clr Chen
When enabling cpufreq-hw driver, it is required for MCUPM to access secure registers. Therefore, we enable side-band to allow MCUPM to access the secure registers. BUG=b:236331463 TEST=It works well after boot to login shell. Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69088 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-11-04mb/google/rex: Fix fw_config probe for UFC and WFCKapil Porwal
Fix fw_config probe for UFC and WFC. BUG=b:255971791 TEST=Build Google Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5103e7da04004414d96f42057c105cf9fbf51b25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04util/cbmem: Update formatting for cbmem -l commandMartin Roth
Some of the cbmem area names have gotten longer, and were making the output of cbmem -l look bad, so expand the name area to 20 characters. Instead of printing a blank area if the name isn't recognized, call it unknown. Change the method of printing the title to match the way the actual text of the table is printed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04soc/intel/**/fast_spi.c: Drop spurious whitespaceAngel Pons
Drop 1 (one) newline and 1 (one) space. Change-Id: I1972d173f99507dd167bd86c73d99434b04701ab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69167 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04commonlib: Fix AMD MP2 BUFFER idMartin Roth
Cut and paste error. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Iae6213ac99bc5c64fd5dcd681c7922eafa011fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69165 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04mb/google/brya/var/lisbon: update USB topology in devicetreeKevin Chiu
update USB topology per the schematic design BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2976028d3efa20e25deedb34ffb8b3bab43b5f5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-04mb/system76/adl-p: Add Darter Pro 8Tim Crawford
The Darter Pro 8 (darp8) is an Alder Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - M.2 SATA SSD (with WDS100T2B0B) - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Windows 10 and Linux 6.1 - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined header + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 5.18.5 - Internal flashing with flashrom v1.2-703-g76118a7c10ed Not working: - Detection of devices in TBT slot on boot Change-Id: Icc84d6cc3aec7149d9b538305288bbe2b56d53e4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04mainboard: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Iccb7f28a2c913ae0983bf224a03610d7fdd13c68 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/intel/skylake: Clean up includesElyes Haouas
Change-Id: I505ef39487b2677993423e5952b54e008e24fcc5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers"Liju-Clr Chen
This reverts commit a8172c329fe309f3b5b409c1a59a227186400dd4. In the aforementioned patch, we allowed MCUPM to access secure registers and set the domain to DOMAIN_2. Additional attribute settings are also required when a hardware is set to a specific domain. Otherwise, there would be violation between hardware. Since MT8188 is in bring-up stage, we simply enable access register permission for the DOMAIN_0 by default. So remove the wrong setting for MCUPM, SCP and SSPM. We will complete DEVAPC setting when the settings are confirmed. Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69139 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-04soc/amd: Specify memory types supported by each chipMartin Roth
This change disables support for memory types not used by each of the chips. This will in turn remove the files for those memory types from the platform builds. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/common: Only call into enabled memory typesMartin Roth
Don't call into disabled memory type code, it won't work. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie239039b3dd2b5d0a6f8e9230fd3466bb8309761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04nb/intel/pineview: Specify supported memory typesElyes Haouas
Change-Id: If40010abdf180e40c2aab7a991c7382dc5b2d7d5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04nb/intel/x4x: Specify supported memory typesElyes Haouas
Change-Id: I07c24ece29616fa008da0935c3fe71e35f16ed2d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04nb/intel/sandybridge: Specify supported memory typesElyes Haouas
Change-Id: Ie43e818d03f411733e1bba5b7a4721c9a54ff4a4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04nb/intel/gm45: Specify supported memory typesElyes Haouas
Change-Id: I3a3a45a1a36ea6ad0b8fb2d3ee78add0b38460ac Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04nb/intel/i945: Specify supported memory typeElyes Haouas
Change-Id: I3cc2a9786dfb1f8fb1ec8e78bde7c46c07f8da48 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04device/dram: Add kconfig options for memory typesMartin Roth
Currently, we're building support for all memory types into every board, and letting the linker remove anything that isn't needed. This is okay, but it'd be nice to be able to build in just what's actually needed. This change adds options to specify both what is used and what is not. By doing it that way, the default values don't change, but platforms can start removing support for memory types that are not needed. When all platforms (SoCs, CPUs and/or Northbridge chips) specify what memory types they support, the defaults on the options to use a particular memory type can be set to no, and the options not to use a memory type can be removed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I07c98a702e0d67c5ad7bd9b8a4ff24c9288ab569 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04checkpatch: add Co-authored-by to signature listMichael Niewöhner
Co-authored-by is commonly used for changes that have more than one author. Add it to the list to make Jenkins happy. Change-Id: I7f66824febe3be756c64ebf44c94bc653a66f1e1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-11-03Revert "cpu/x86/mp_init.c: Set a bogus initial lapic_id"Felix Held
This reverts commit 1bb9786da30e ("cpu/x86/mp_init.c: Set a bogus initial lapic_id"), since it breaks MP init on amd/mandolin: [INFO ] CPU #0 initialized [INFO ] Initializing CPU #3 [INFO ] Initializing CPU #1 [INFO ] Initializing CPU #2 [EMERG] CPU: missing CPU device structureCPU: vendor AMD device 810f81 [DEBUG] CPU: family 17, model 18, stepping 01 [DEBUG] microcode: patch id to apply = 0x08108109 [INFO ] microcode: being updated to patch id = 0x08108109 succeeded [INFO ] CPU #1 initialized [ERROR] MP record 3 timeout. [INFO ] bsp_do_flight_plan done after 1206 msecs. [ERROR] MP initialization failure. [EMERG] mp_init_with_smm failed. Halting. TEST=The board boots again with the revert applied Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic1cae88f7345f9ff79e8f6e574521095b57c8cb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69186 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03cpu/x86/mp_init.c: Handle failed init_bsp()Arthur Heymans
Bail out of mp_init if this function fails. Change-Id: I7be5d6c32458ba98f4f8c5c9340790ff989c91e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69109 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03cpu/x86/mp_init.c: Set a bogus initial lapic_idArthur Heymans
This makes it easier to catch errors later if the ap_init code fails to properly set things up. Change-Id: I938faf042bfa4fe1fc39e78ab740c9b210bc105c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69108 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-11-03soc/amd/glinda/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields, updated per glinda ppr #57254, rev 1.51 Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I509eaf5910d8d65ce0956200d7c00451ff9ce864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/morgana/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields, updated per morgana ppr #57396, rev 1.52 Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/mendocino/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I01dcea783542ecc0a761191907c1273016f854c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/picasso/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/cezanne/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib5045812fb05eb8c3fb818d807e34decf69c6fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/69068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/*/data_fabric: move data_fabric_set_mmio_np to commonFred Reitberger
The data_fabric_set_mmio_np function is effectively identical, so move it to common code. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03util/docker/coreboot.org-status: Rewrite parserPatrick Georgi
The current tool is a shell script that mixes data collection and HTML generation and is generally a pain to work with. It takes 15 minutes to run. The new tool is written in go, collects all data first, then generates the output HTML from the data and a single template, and finishes in 10 seconds. The goal in this version is to produce output as similar as possible to the output of the shell script. Some difference will remain because the shell script returns some trash data whose reproduction would require more effort than is worth. Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2022-11-03{device,drivers}: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I1727bf56b4090d040aab413006dec7aca0587d44 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03treewide: Add 'IWYU pragma: export' commentElyes Haouas
This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented headers. Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-03include/acpi/acpi_crat.h: Add missing <stdint.h>Elyes Haouas
Change-Id: Ic157cd820be204035706f8074dd6dbcb95c0f04f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-03ec/google/wilco: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I93f02674fde0415e4d831ec13541a806bbc3bd91 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-11-03test/lib: Add non-existent DIMMs test case in spd_cache-testEric Lai
Add non-existent DIMMs test case in spd_cache-test. BUG=b:213964936 TEST=make unit-tests PASSED Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3c8aa92ee0cfd5908399f4bbd305f8f306571d40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-03mb/google/brya/gaelin: Configure GPIO settingsRaymond Chung
Override GPIO pad configuration based on the latest gaelin schematic. BUG=b:249000573 BRANCH=firmware-brya-14505.B TEST=FW_NAME=emerge-brask coreboot Change-Id: I649ac5131393008787cbb403fc64b914de23312b Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-03soc/intel/alderlake: Hook up GMA ACPI brightness controlsTim Crawford
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/lemp11. Backlight controls work on Windows 10 and Linux 6.1. Change-Id: I1cc33bf0121ff44aea68a7e3615c5e58e2ab6ce2 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03mb/ocp/deltalake: Revert OVERRIDE_UART_FOR_CONSOLEJohnny Lin
This reverts commit f6efeae66c (mb/ocp/deltalake: Override uart base address via VPD variable). Both SOL and UART would use 0x2f8, disabling it can also avoid searching flash VPD during each UART tx. Change-Id: I453fdddbb883eb956bac708913c17bb581f75b9d Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03mb/google/skyrim: Disable SD ASPMEricKY Cheng
Disable ASPM on SD until b/245550573 is root-caused/fixed. Logical_lane 1 on winterhold is EMMC device. Disable ASPM for suspend issue. BUG=b:249914847, b:245550573 TEST=emerge-skyrim coreboot chromeos-bootimage and test on whiterun proto emmc sku with suspend_stress_test -c 10 Change-Id: If080cdb517a3f22aa89c8053fb6bba9e931c6f76 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68940 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-03tests: Add option for debug symbols & no optimizationMartin Roth
To make it easier to build the tests with debug symbols, add a check for the "GDB_DEBUG" environment variable. If set, build with -g and -Og to enable the symbols and disable optimization. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3a644dcccb7e15473413b775da8f70617afaefce Reviewed-on: https://review.coreboot.org/c/coreboot/+/67918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-03drivers/i2c/generic: Tweak error text for missing HIDMatt DeVillier
- drop ERROR prefix since already provided by cbmem log - make error text more clear about cause of error BUG=none Change-Id: I1795aee240a5383b21108c697e930a2e4972a0b4 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69062 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-03nb/intel/gm45: Make polling loops more explicitAngel Pons
Replace `while (...);` with `do {} while (...);` so that it's easier to distinguish polling loops from something else, like function calls. The `{}` can be understood as "nothing", so that the construct is naturally read as "do nothing while (...)". Another reason to prefer this method is that Jenkins does not complain. Change-Id: Ifbf3cf072f8b817b2fdeece4ef89bae0822bb6e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-02util/eventlog: Correct the capitalization for diagnostics typesHsuan Ting Chen
Correct the capitalization of ELOG_CROS_DIAG_TYPE_STORAGE_HEALTH from "Storage Health Info" to "Storage health info", which is already widely used in depthcharge diagnostics tools. BUG=b:254405481 TEST=none Change-Id: Ia6c1df9e8d2ee6f8ae11b962e76b52f3c6663c42 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-02mb/google/skyrim: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on skyrim, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. Change-Id: Id9e3089decf0f94a1358929684ce248e52cbe41f Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-11-02util/cbfstool: fix memory leak in compress.cSolomon Alan-Dei
free the memory allocated in lz4_compress function before returning from it. Reported-by: Coverity (CID:1469433) Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com> Change-Id: I8698090d519964348e51fc3b6f2023d06d81fcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-02mb/google/hatch/var/kohaku: ensure FPMCU is power cycled on resetTarun Tuli
Leakage from the SPI CS line onto the FPMCU VDD rail was preventing the FPMCU from fully shutting down on AP reset. Instead of simply turning off the power rail, now ensure the CS line is not driven high until late in coreboot. This ensures it is completely off for the requisite minimum of 200ms (now measured at approx 1100ms). BUG=b:245953688 TEST=Confirmed FPMCU is still functional on Kohaku. Confirmed FpRebootPowerCycle unit test now passes BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1e7e32f61c3ac1b3154d42821cc1dd4c5d3de303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68819 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/hatch: Add variant finalize support for hatch devicesTarun Tuli
Provide a variant_finalize() method and call to be invoked from mainboard_ops.final BUG=b:245953688 TEST=Hatch and variants build BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I9253ed4be1b08d0c7f65526c9b26dbcd00ffccc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68821 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/brya/var/lisbon: Enable SaGvKevin Chiu
Enable SaGv support for lisbon BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot pass RMT verification Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ic7d3203bfe06973b023a38d1aa3d69cce5c3a60c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69013 Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot diskKevin Chiu
Support GL9763E as a eMMC boot disk BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ibe579a913225b5241412bbb1b8ea995a5102a3bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/brya: enable PCIe RP12 for lisbon eMMC supportKevin Chiu
BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ief8ca9cf845156ac761556d0eb49edb65894c001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/corsola: Add new board 'voltorb'Mars Chen
Add a new kingler follower 'voltorb'. BUG=b:256737049 TEST=emerge-corsola coreboot Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com> Change-Id: Ic7175c38fcde76ab0360f62da161994ba2ee6a69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-02mb/clevo/l140mu: work around PECI staying high when idle, blocking s0ixMichael Niewöhner
According to Intel doc# 575683 the PECI bus should be low when idle and is pulled up by clients with strong drive. However, for unknown reasons the bus stays high on this board, blocking s0ix entry. The PECI reference schematic in the ASPEED AST2400 BMC datasheet (actually not related to this board) says that a pull-down is *required* for the idle state. This might be just a requirement of this BMC, since this is nowhere documented in Intel datasheets, schematics or elsewhere. However, configuring a weak pull-down (20 k) on the PECI pad indeed solves this problem for now. Change-Id: I85193000af67cd2c0465bdbb58cdd51b68fd5b4f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/clevo/l140cu: work around PECI staying high when idle, blocking s0ixMichael Niewöhner
According to Intel doc# 575683 the PECI bus should be low when idle and is pulled up by clients with strong drive. However, for unknown reasons the bus stays high on this board, blocking s0ix entry. The PECI reference schematic in the ASPEED AST2400 BMC datasheet (actually not related to this board) says that a pull-down is *required* for the idle state. This might be just a requirement of this BMC, since this is nowhere documented in Intel datasheets, schematics or elsewhere. However, configuring a weak pull-down (20 k) on the PECI pad indeed solves this problem for now. Change-Id: Ib5a6b0ad3553c2cf795037d6a1982102bcb04644 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68793 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/clevo/l140cu: enable S0ixMichael Niewöhner
Enable S0ix for the board, as done in vendor fw. Change-Id: Ifdf93e1e599e7cc03fc02297eafb49d34b1f6172 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68792 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02soc/intel/common: provide display hook in PEP for ECsMichael Niewöhner
Provide PEP display notification hook for ECs. Change-Id: Icbfd294cdd238e63eb947c227a9cf73daca702ef Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-02acpigen: export acpigen_write_field_nameMichael Niewöhner
It will be used in a follow-up change. Change-Id: If89f9569c33949995d3b45a5f871ff2cb84a6610 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-02util/release/build-release: Use bash arrays for paramsMartin Roth
Instead of using unquoted strings for the command line parameters, use arrays which naturally split into separate elements inside the quotes. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1c96d5072b98523af4e407cfff8f4d1d28ec3297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-02device/mmio: add clr/setbitsXp macrosMichael Niewöhner
Add clr/setbits*p macros as pendant to read/write*p. Change-Id: I5b10ccab97c3a372051050b28ada854baec91d18 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68790 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02soc/intel/common/acpi: provide PTS/WAK hooks for ECsMichael Niewöhner
Provide PTS/WAK hooks for ECs like we do for mainboards. Change-Id: I687254362a896baa590959bd01ae49579ec12c94 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68788 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02payloads/grub: Work around entry point issueArthur Heymans
With -Os grub-mkimage does not create an elf with the correct entry point because some parts of the elf images are placed in .text.unlikely. The linker does not know where to place that and places it below .text, hence messing up the entry point. To avoid this use the compiler flag -fno-reorder-functions. Change-Id: Ic4a12f45d30b781870faa38575e8b2c10e0a42e8 Resolves: https://ticket.coreboot.org/issues/343 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64235 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Hackware <human@hackware.cl> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/brya/var/gladios: use RPL FSP headersKevin Chiu
To support an RPL SKU on gladios, gladios must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for gladios so that it will use the RPL FSP headers for gladios. BUG=b:239513596 BRANCH=None TEST=FW_NAME=gladios emerge-brask intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ic30f7fe30eb0a3151cdf46fff609819056b2fbfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/68570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/skyrim: Select GOOGLE_SMBIOS_MAINBOARD_VERSIONAmanda Huang
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:256723358 TEST=1. emerge-skyrim coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Change-Id: I97295083dbca1c285ef7359d86abac7315c654c9 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69087 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-02mb/google/rex: Disable TBT PCIe rp1 and rp3 root portszhaojohn
Rex board only uses TBT PCIe root ports 0 and 2. This change disables rp1 and rp3 root ports. BUG=b:254207628 TEST=Booted to OS and verified rp1 and rp3 root ports were disabled. Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68854 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-01mb/{lenovo,packardbell}: Enable MEI deviceEvgeny Zinoviev
Enable the MEI in device trees of some Ibex Peak, Cougar Point and Panther Point boards where they have been disabled. Change-Id: I4327d19d3ed1a93a6466057f6eceed49ab9441c5 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2022-11-01mb/google/brask/variants/moli: remove fan settingRaihow Shi
Disable Active Policy and remove fan setting to let ec control fan indenpendently. BUG=b:236294162 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ie8851800d30ebf4d948d6eaadda2387c8afe52d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-31drivers/ipmi/ipmi_kcs_ops.c: accommodate BMC revision being 0Jonathan Zhang
BMC major/minor revision may be 0. Get the value directly from BMC without checking to accommodate such situation. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I0e08c6d02de8f6efceb69b6d6cebad9d61cfd20e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68685 Reviewed-by: Shuming Chu (Shuming) <s1218944@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-31drivers/ipmi/ipmi_ops.h: add __packed to sel_rec structsJonathan Zhang
Align with BMC on the SEL record format. Change-Id: Icfcef684caa253663503eadffc819ad2ab65550f Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68757 Reviewed-by: Shuming Chu (Shuming) <s1218944@gmail.com> Reviewed-by: TangYiwei Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-30mb/google/skyrim: Implement touchscreen power sequencingMatt DeVillier
Assuming variants have a touchscreen by default, set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. Variants/SKUs which do not have a touchscreen (if any) can use the romstage/ramstage GPIO override tables to set the associated enable/ reset GPIOs to NC. BUG=b:121309055 TEST=build/boot skyrim with rest of patch series Change-Id: Ic4d7ac8f951bb94da2216a24dc85a96275c9d449 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-30util/kconfig: Uprev to Linux 6.0's kconfigPatrick Georgi
Only minor changes in kconfig this time that shouldn't affect us. TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains the same Change-Id: I77cc8517128a973c345c41da2c483b78eeaee89f Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30util/kconfig: Uprev to Linux 5.19's kconfigPatrick Georgi
Only minor changes in kconfig this time that shouldn't affect us. TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains the same Change-Id: Icc83c929dd1ea2d98e1a789560ce26886ded1f12 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30util/kconfig: Uprev to Linux 5.18's kconfigPatrick Georgi
Only minor changes in kconfig this time that shouldn't affect us. TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains the same Change-Id: I46f43182ce9ec1b6a5923cb77dcd6e335e44c87a Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30util/kconfig: Uprev to Linux 5.17's kconfigPatrick Georgi
Another upstream refactoring, another local patch gone! TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains the same Change-Id: I0f99dcbd8ecc7256551f0a6e2c83c060cb1999b6 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30util/kconfig: Uprev to Linux 5.16's kconfigPatrick Georgi
Linux 5.16 saw a significant rewrite in the boolean handling which reduces our change set. On the other hand, it's all new code. Comparing the config.build and config.h files generated by `util/abuild/abuild -C`, only a few lines of comment in the header changed. Change-Id: I52984e15a48236ddf228707aec85e90f71aa4382 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30MAINTAINERS: Make Misc FixesMartin Roth
- X86 architecture is maintained, so mark it as such. - Legacy AMD chips are supported for odd fixes. - Remove maintainers whose emails are bouncing. - Remove maintainers who don't have +2 rights in gerrit. - According to the instructions, we should use S: Orphan, not Orphaned. - Update incorrect email addresses. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib6d47a8c34482c81ff96dbeec760852cba01dabc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-30MAINTAINERS: Update EC sectionMartin Roth
- Presumably all of the ec/google subdirectory is maintained - Add list of Orphan ECs Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia93e8da9898903ae92873a07fb0af2a2aa76e8b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-30MAINTAINERS: Update mainboardsMartin Roth
- AMD reference boards are maintained at least for odd fixes. - Google panther has become a variant of Beltino, so remove it. - Remove people whose email addresses are bouncing email. - Remove people who responded to my email about being a maintainer and asked to be removed. - Alphabetize list Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic6ecaae77df2f2edaf724160bce04c038cbd115e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-30MAINTAINERS: Add orphaned mainboardsMartin Roth
The mainboards are broken out into individual entries in hopes that it will be easier for someone to claim ownership than if they were lumped into a single "Orphaned Mainboards" group. The theory behind this is that a single mainboard is really the easiest piece of coreboot to maintain. Hopefully some less-experienced people will be interested in stepping up to take over ownership of a mainboard. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9542b3a7cd87fa8656bc0982c08061e9d0513745 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-29mainboard/amd/chausie: Don't use APCB_FT6_UpdatableNikolai Vyssotski
This APCB binary is not used for coreboot builds. Coreboot does not support RW APCB. Change-Id: I4d317ae31cf226b5481619f1539abb6237033f7c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29Docs/releases: Update release checklist documentMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9a79cf92620755e19266faaf593dc2657acdb16f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29soc/amd/common: Initialize STB Spill-to-DRAMMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I547671d2bcfe011566466665b14e151b8ec05430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29commonlib...cbmem_id.h: Add AMD STB buffer IDs for CBMEMMartin Roth
- CBMEM_ID_AMD_STB Main Spill-to-DRAM buffer. 2 to 16MiB. - CBMEM_ID_AMD_MP2 Debug buffer. 128KiB Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I27157ad65df992bcdd0e0d15a6d01b96e24067c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-29soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB deviceFelix Held
Don't set bit 2 in _STA in order for Windows not to show a warning about an unknown device in the device manager for this device. Since the _STA object just returns a constant, a name definition can be used instead of a method definition. TEST=The unknown device with device instance path ACPI\AAHB0000\0 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Just shutting down and then booting it again won't clear some internal state in Windows, so a reboot is needed instead for the change to become visible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-29util/lint: fall back to regular grep in kconfig_lintSolomon Alan-Dei
Automatically fall back to using regular grep if working outside a git repository and the option to use regular grep is not specified Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com> Change-Id: I0cdecf01a0e74c30947c4fe7e7c7d9457a5165a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-29mb/starlabs/*: Change the local version to KconfigSean Rhodes
Replace the string with a Kconfig option Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib11ddd04c44f47b94f4fc9eaed278d554d581b0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-29mb/siemens/mc_ehl: Remove spd.bin from CBFSWerner Zeh
The SPD data for DRAM init has moved into the hwinfo data structure and is therefore not used from spd.bin anymore. spd.bin will not receive any updates, changes will only be done in hwinfo. There is no reason to keep spd.bin around so remove it for both variants. Change-Id: Ie6091b655ba7ff2e01b684266ce34b85593b8623 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-29soc/intel/meteorlake: Move P2SB PCI resource into P2SB deviceSubrata Banik
This patch ensures the P2SB PCI device resource is getting reserved so that the resource allocator is not assigning this resource to any other PCI device during the PCI enumeration. BUG=b:254207628 TEST=Able to ensure on the Google/Rex device, the PCI enumeration is not assigning the P2SB BAR (0xE000_0000) to TBT Root Port3. Instead the 0xE000_0000 address is being assigned to the P2SB PCI device. Without this patch: [SPEW ]     PCI: 00:07.3 resource base e0000000 size c200000 align 20 gran 20 limit ec1fffff flags 60080202 index 20 [DEBUG]      GENERIC: 1.0 [DEBUG]      NONE [SPEW ]      NONE resource base e0000000 size c200000 align 12 gran 12 limit ec1fffff flags 40000200 index 10 With this patch: [SPEW ]     PCI: 00:07.3 resource base e1000000 size c200000 align 20 gran 20 limit ed1fffff flags 60080202 index 20 [DEBUG]      GENERIC: 1.0 [DEBUG]      NONE [SPEW ]      NONE resource base e1000000 size c200000 align 12 gran 12 limit ed1fffff flags 40000200 index 10 ...... [DEBUG]     PCI: 00:1f.1 [SPEW ]     PCI: 00:1f.1 resource base e0000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib0789b442af23f6be81c666e284633ef342dffe0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-29soc/intel/common: Fix potential NULL pointer dereferenceShaik Shahina
BUG=NONE TEST=Boot to OS on Nivviks Change-Id: I154011963e945b54dfca07f884e473d44dc4e813 Signed-off-by: Shaik Shahina <shahina.shaik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68903 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-29mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHzAlanKY Lee
Fine tune I2C3 clock frequency under the 400 kHz. From 402.7 kHz to 382.9 kHz. BUG=b:255505160 BRANCH=firmware-brya-14505.B TEST=FW_NAME="skolas" emerge-brya coreboot chromeos-bootimage measure by scope with skolas Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-20 14:52:30 +0000