diff options
| author | AlanKY Lee <alanky_lee@compal.corp-partner.google.com> | 2022-10-27 16:43:24 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-10-29 02:42:43 +0000 |
| commit | bf2f6e27297571da6d15ad93dd71bf0c0b38281b (patch) | |
| tree | 738efcceea61343d5cdb349caabe28dcc4b46368 | |
| parent | 1799290ea2bb628516485bfb14a7fb809c21e5f9 (diff) | |
mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHz
Fine tune I2C3 clock frequency under the 400 kHz. From 402.7 kHz to
382.9 kHz.
BUG=b:255505160
BRANCH=firmware-brya-14505.B
TEST=FW_NAME="skolas" emerge-brya coreboot chromeos-bootimage
measure by scope with skolas
Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/skolas/overridetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb index 110ca42e1a..fe60e90dfc 100644 --- a/src/mainboard/google/brya/variants/skolas/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb @@ -95,7 +95,7 @@ chip soc/intel/alderlake }, .i2c[3] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, + .rise_time_ns = 600, .fall_time_ns = 400, .data_hold_time_ns = 50, }, |