From bf2f6e27297571da6d15ad93dd71bf0c0b38281b Mon Sep 17 00:00:00 2001 From: AlanKY Lee Date: Thu, 27 Oct 2022 16:43:24 +0800 Subject: mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHz Fine tune I2C3 clock frequency under the 400 kHz. From 402.7 kHz to 382.9 kHz. BUG=b:255505160 BRANCH=firmware-brya-14505.B TEST=FW_NAME="skolas" emerge-brya coreboot chromeos-bootimage measure by scope with skolas Signed-off-by: AlanKY Lee Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68906 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro Reviewed-by: Eric Lai --- src/mainboard/google/brya/variants/skolas/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb index 110ca42e1a..fe60e90dfc 100644 --- a/src/mainboard/google/brya/variants/skolas/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb @@ -95,7 +95,7 @@ chip soc/intel/alderlake }, .i2c[3] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, + .rise_time_ns = 600, .fall_time_ns = 400, .data_hold_time_ns = 50, }, -- cgit v1.2.3