diff options
| author | Martin Roth <gaumless@gmail.com> | 2022-10-29 16:00:57 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-04 01:00:22 +0000 |
| commit | b6877e401a8686ac6dfcebb1184ebdfabad6f3e6 (patch) | |
| tree | 4406901ff3bad50166907a1467883a167765f297 | |
| parent | f2503fce3fbfa33fbb50b37a99234d96a83c6156 (diff) | |
soc/amd/common: Only call into enabled memory types
Don't call into disabled memory type code, it won't work.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie239039b3dd2b5d0a6f8e9230fd3466bb8309761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/soc/amd/common/fsp/dmi.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index b443fe2533..fd2a8e4064 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -23,18 +23,17 @@ */ static uint16_t ddr_speed_mhz_to_reported_mts(uint16_t ddr_type, uint16_t speed) { - switch (ddr_type) { - case MEMORY_TYPE_DDR4: + + if (CONFIG(USE_DDR4) && ddr_type == MEMORY_TYPE_DDR4) return ddr4_speed_mhz_to_reported_mts(speed); - case MEMORY_TYPE_LPDDR4: + else if (CONFIG(USE_LPDDR4) && ddr_type == MEMORY_TYPE_LPDDR4) return lpddr4_speed_mhz_to_reported_mts(speed); - case MEMORY_TYPE_DDR5: - case MEMORY_TYPE_LPDDR5: + else if (CONFIG(USE_DDR5) && (ddr_type == MEMORY_TYPE_DDR5 || + ddr_type == MEMORY_TYPE_LPDDR5)) return ddr5_speed_mhz_to_reported_mts(speed); - default: - printk(BIOS_ERR, "Unknown memory type %x\n", ddr_type); - return 0; - } + + printk(BIOS_ERR, "Unknown memory type %x\n", ddr_type); + return 0; } /** |