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2023-03-30console: Deselect using ANSI escape characters when SimNow is usedZheng Bao
To remove the annoying "ESC [1m" at SimNow console window. Change-Id: I300aee946f342f41b94288b75b843956de9d3e88 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-30mb/prodrive/atlas: Rework EEPROM layout structuresAngel Pons
To avoid having to calculate the length of a struct separately, rework the code to give the struct a tag name, so that `sizeof()` can be used instead. This involves refactoring the `get_emi_eeprom_vpd()` function to return a struct instead of a union, so callers can no longer access the EEPROM data as an array of bytes without additional code, but this array view is only used inside `get_emi_eeprom_vpd()` when reading the data from EMI. Change-Id: Id1bc40939631baa131b5f60eadbfe42838294ebe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-30soc/intel/alderlake: Avoid reprogramming the SRAM BARSubrata Banik
This patch avoids the redundant programming of SRAM BAR when the SRAM PCI device is enabled. Rather read the PCH SRAM Base Address Register while enabling crashlog feature. Additionally, this patch relies on PCI enumeration to get the SRAM BAR rather than hijacking the SPI temporary base address which might have resulted in problems if SPI is disabled on some platform with BAR being implemented. TEST=Able to build and boot google/marasov and crashlog is working. Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-30mb/google/nissa/var/yavilla: Disable storage devices based on fw_configTony Huang
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:273791621 TEST=emerge-nissa coreboot Change-Id: I1a6013e0ad0c430d83bbbad4b92392c8c4815b0d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-30mb/google/nissa/var/yavilla: Update devicetree settingTony Huang
Update devicetree according to yavilla's design. Add Kconfig for TPM I2C bus. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I1b44436a7f93d62764d0451c738ae33976a24a15 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-03-30mb/google/skyrim: Use die_no_apcbFred Reitberger
Use die_no_apcb to cause a build error when the APCB or SPD sources are not found. TEST=builds with and without matching APCB and SPD sources Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I62dce2c71061bfc5c01e0344b7dc115a47669140 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29mb/google/skyrim: Get ready to add MP2 firmwareMartin Roth
This sets the location of the skyrim MP2 firmware within the mainboard's blobs directory, and adds the Kconfig option to the mainboard directory so that it can be enabled in a saved .config file. The skyrim MP2 firmware is skyrim specific, so it should not be placed in the main PSP AMD_BLOBS directory. We will also only want to enable the MP2 firmware for chromeos builds as it's not useful for non-chromeos builds. BUG=b:259554520 TEST=Build MP2 firmware into image, see that it gets loaded BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I04be6f2d0b605d4eca37fd927a70310259dc106c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-29soc/amd/stoneyridge: use common AMD CPU power state ACPI generationFelix Held
Instead of using the PSTATE SSDT generated by binaryPI, use the common AMD code by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE. To match the SSDT from binaryPI, set ACPI_SSDT_PSD_INDEPENDENT to n. There are two differences to the binaryPI SSDT: Now coreboot includes the C1 state in the _CST package instead of just having the kernel add this due to the ACPI_FADT_C1_SUPPORTED bit being set and the address of the PS_STS_REG P state status MSR is written to the corresponding field of the _PCT package instead of being 0. TEST=On Careena the new P and C state ACPI packages are nearly identical to the ones from the SSDT from binaryPI with the two functional differences mentioned above. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icdf6bc8f0e0363f185a294ab84edcb51322e7eb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/cpu: implement get_pstate_latencyFelix Held
Both the algorithm and the registers involved are described in the public version of BKDG #55072 Rev 3.09 in chapter 2.5.2.1.7.3.2 _PSS (Performance Supported States). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b2c177d9d80c5c205340f3f428186d6b8eb7e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/picasso/Kconfig: update help text for 2nd VBIOS ID detectionFelix Held
The help text for VGA_BIOS_SECOND_ID was outdated and from a time before we found out that just looking at the CPUID doesn't reliably tell us on which type of silicon we're running and which VBIOS file to pick, so we had to use a different method. Update the help text to match what the code does. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia568771ed7dfa0c7bb850b0efcd2959d7ddfd4a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73335 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/acpi/cpu_power_state: introduce & use get_pstate_latencyFelix Held
On the Zen-based CPUs, the transition and bus master latency are always written as 0, but on but on Stoneyridge hardware-dependent values are used. Introduce get_pstate_latency that returns 0 for all non-CAR AMD CPUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81086fa64909c7350b3b171ea6ea9b46f1708f67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge: implement and use get_pstate_0_regFelix Held
Introduce get_pstate_0_reg and use it in tsc_freq_mhz to get the P state register number corresponding to P state 0. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b92a858bf36b04a570d99c656e5ccfc84457724 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/acpi/cpu_power_state: introduce and use get_pstate_0_regFelix Held
On the Zen-based CPUs, P state 0 corresponds to the first P state MSR, but on Stoneyridge this isn't the case. Introduce get_pstate_0_reg that returns 0 for all non-CAR AMD CPUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icc11e5b6099d37edb934e66fe329d8013d25f68d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/acpi/cpu_power_state: factor out get_visible_pstate_countFelix Held
Factor out the MSR access into a function with a more descriptive name. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I331c3205390edcbd8749b2d52b7cc7ac3a8ced5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/acpi: add C state config tableFelix Held
The C state ACPI packages binaryPI generates and passes to coreboot in the PSTATE SSDT only include the C2 state, but the kernel will add the C1 state to its usable C states in this case. The native C state code will generate both the C1 and C2 state packages to be more complete and also to be more in line with the other AMD SoCs. The code added in this commit isn't used yet, but will be used as soon as Stoneyridge will be using the common AMD generate_cpu_entries by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE once all needed helper functions are implemented for Stoneyridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06f90306ac196704e0102d0da6eab03f51513c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/block/cpu/Kconfig: drop FAM17H_19H suffix from TSC optionFelix Held
The SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option is valid for all SoCs with Zen-based CPU cores including the family 1Ah, so remove the suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I58d29e69a44b7b97fa5cfeb0e461531b926f7480 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/block/cpu/tsc_freq: move static variable inside functionFelix Held
Move the static mhz variable inside the only function that is accessing it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief98c0a1c35fe1bbc4ff38dd175f12e0b3ddc515 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/block/cpu/tsc/tsc_freq: use get_pstate_core_freqFelix Held
Use get_pstate_core_freq instead of open-coding the calculations in tsc_freq_mhz. In the case of the CPU frequency divider being 0, get_pstate_core_freq will return 0; in this case that shouldn't happen, TSC_DEFAULT_FREQ_MHZ will be used as frequency, since for the TSC frequency it's better to err on the end of the expected frequency being too high which will cause longer than expected delays instead of too short delays. Now that the code is using get_pstate_core_freq, this code is valid for Glinda too, so also remove the comment on the SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option being selected in the Glinda Kconfig. This Kconfig option will be renamed in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I01168834d4018c92f44782eda0c65b1aa392030d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/tsc_freq: use get_pstate_core_freqFelix Held
Use get_pstate_core_freq instead of open-coding the calculations in tsc_freq_mhz. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If5d526e6b365c62a6669241f4fcdd25eca3f15fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/cpu/tsc: add get_pstate_core_freq for family 15h and 16hFelix Held
This function will be used in follow-up patches for both the TSC rate calculation and the still to be implemented P state ACPI table generation in coreboot. The was checked against BKDG 52740 Rev 3.05, BKDG #55072 Rev 3.04, and BKDG #50742 Rev 3.08. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9afaa044da994d330c3e546b774eb1f82e4f30e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/cpu/tsc: factor out family-specific get_pstate_core_freqFelix Held
Factor out the get_pstate_core_freq function from the SoC's acpi.c files to both avoid duplication and to also be able to use the same function in the TSC frequency calculation in a follow-up patch. The family 17h and 19h SoCs use the same frequency encoding in the P state MSRs while the family 1Ah SoCs use a different encoding. The family 15h and 16h SoCs use another encoding, but since this isn't implemented in Stoneyridge's acpi.c, this will be added in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8619822c2c61e06ae5db86896d5323c9b105b25b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/monotonic_time: add comment that we can't use TSCFelix Held
Due to a non-constant TSC rate before the microcode update is applied, the Performance Time Stamp Counter is used instead. To clarify this, add a comment to the timestamp_get implementation. See commit 24079323d4d8 ("soc/amd/stoneyridge: provide alternate monotonic timer") and the description of the TscInvariant bit in CPUID Fn8000_0007_EDX Advanced Power Management Information in the public version of BKDG #55072 Rev 3.09 for more details. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I824b372c36fa6f3eb912469b235a9474f6a58ff5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29mb/google/skyrim/var/winterhold: adjust the eDP panel power sequenceChris.Wang
set pwr_on_varybl_to_blon to 0x1c, which means fw will delay 112ms between backlight on and vary backlight. BUG=b:271704149 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on whiterun Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ib966d2ebd4ef4a8085695901ec5da160f467e32e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-29soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustmentChris.Wang
Add UPD parameter for eDP power sequence adjust. The pwr_on_vary_bl_to_blon is set one unit per 4ms. BUG=b:271704149 TEST=Build; Verify the UPD was pass to system integrated table; measure the power on sequence on whiterun Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I25c9f962e70f599c780259f0943a03f8aa7cbfd1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-29vc/amd/fsp/mendocino/FspmUpd: Update UDP structure for MDN-FSPChris.Wang
Update UPD structure to align with MDN-FSP. BUG=b:271704149 BRANCH=none TEST=Build/Boot to Chrome OS Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie4021cebb57e3ec22191486aafd9099eec0fbd99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-29arch/x86/smbios: Add socket type for Meteor LakeJay Patel
Add socket type for Meteor Lake as PROCESSOR_UPGRADE_OTHER. BUG=None TEST=processor upgrade is equal to "Other" for "dmidecode -t 4" Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: If891990436a0679697e292b460eaec63c09e7bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29mb/google/rex/Kconfig: Add SMBIOS mainboard version flagJay Patel
Add GOOGLE_SMBIOS_MAINBOARD_VERSION flag for rex board. BUG=None TEST=Verfied board ID for rex using "crossystem" command, giving the output as 1. Without CL: localhost ~ # crossystem arch = x86 # [RO/str] Platform architecture backup_nvram_request = 1 # [RW/int] Backup the nvram somewh battery_cutoff_request = 0 # [RW/int] Cut off battery and shu block_devmode = 0 # [RW/int] Block all use of develo board_id = (error) # [RO/int] Board hardware revision clear_tpm_owner_done = 0 # [RW/int] Clear TPM owner done With CL: localhost ~ # crossystem arch = x86 # [RO/str] Platform architecture backup_nvram_request = 1 # [RW/int] Backup the nvram somewh battery_cutoff_request = 0 # [RW/int] Cut off battery and shu block_devmode = 0 # [RW/int] Block all use of develo board_id = 1 # [RO/int] Board hardware revision clear_tpm_owner_done = 0 # [RW/int] Clear TPM owner done Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: I644ed7a948f0094a0be080153d83eaa2e37b8f1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74037 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-29Documentation: Add Asus P3B-FKeith Hui
Change-Id: I0cd6141bb8baa082d5558490533649f907f25dd1 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-29Documentation: Add Asus P2B-LSKeith Hui
Change-Id: Ib885c4dd8472ed2b0a61c548f6ef652979a33153 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-29nb/intel/i440bx/debug.c: Refactor newlines and save some printk callsKeith Hui
There are two conditions within the config space dump code, one to print offset, one at the end to put a newline. Tweak the printk strings so the first conditioned printk does it all and move the second printk out of the loop to the very end. Change-Id: Ie9dc744406ba20412892df96720e88e24c3d52bc Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73887 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-29mb/google/brya/var/crota: Add lp5x memory parts for `K3KL6L60GM-MGCT`Terry Chen
Update the mem_parts_used.txt, generate Makefile.inc and dram_id.generated.txt for this part. DRAM Part Name ID to assign K3KL6L60GM-MGCT 5 (0101) BUG=b:267249674 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I20a12a58d8a3d66a901a14569ca710acba3c05f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73920 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-29soc/intel/common: Add Intel Trace Hub driverPratikkumar Prajapati
From Meteor Lake onwards Intel FSP will generate the Trace Hub related HOB if the Trace Hub is configured to save data in DRAM. This memory region is used by Trace Hub to store the traces for debugging purpose. This driver locates the HOB and marks the memory region reserved so that OS does not use it. Intel Trace Hub developer manual can be found via document #671536 on Intel's website. Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-29drivers/intel/fsp2_0: Add API to find FSP resource HOB by GUIDPratikkumar Prajapati
The API finds the FSP resource HOB for the given GUID. Returns the pointer to the HOB if found, otherwise NULL Change-Id: I4ebc9b7d214e5fc731ae45f28e7f5732a7635cbc Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-29soc/intel/cmn/crashlog: Add check for zero based SRAM BARSubrata Banik
This patch adds a check for zero based SRAM base address. It will help to avoid running into problems if the SRAM is disabled and the base address register is zero. TEST=Able to build and boot google/marasov with PCH SRAM being disabled. Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29vc/intel/fsp/mtl: Update header files from 3064_81 to 3084_85Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3084_85, previous version being 3064_81. FirmwareVersionInfo.h: 1. Define INTEL_FVI_SMBIOS_TYPE macro FSPM: 1. Remove deprecated UPD `BclkSource` 2. Address offset changes FSPS: 1. Add `CnviWifiCore` UPD 2. Address offset changes BUG=b:274051289 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I24dea1a31dbb592f9dea4246a3d490e5d23dca9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29mb/google/nissa/var/yavilla: Update GPIO settingShon Wang
Configure GPIOs according to schematics. BUG=b:273791621 TEST=emerge-nissa coreboot Change-Id: I5a522b59468667d20674d55597cc06975bc12ab5 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2023-03-28soc/amd/stoneyridge/graphics: introduce defines for constantsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2021a106e0d3a603b1a05296411700ffea32fc8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28soc/amd/stoneyridge: move map_oprom_vendev to graphics.cFelix Held
Move map_oprom_vendev to graphics.c to match the other AMD SoCs. Also change the comment style to be more in line with the rest of coreboot and drop the unneeded line break in the printk call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icc1f3d73fba973413c5a22e2f5ae01bc58bc3e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28soc/amd/stoneyridge/Kconfig: use correct VGA_BIOS_IDFelix Held
Fix the VGA_BIOS_ID IDs to match the PCI IDs in the VBIOS binaries and the PCI ID Stoneyidge's map_oprom_vendev returns. This fixes the problem that the display wasn't initialized due to not finding the VBIOS file in CBFS. This bug in the Stoneyridge Kconfig was unmasked by commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping in pci_rom_probe"). TEST=Display in Careena lights up again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d1e6a3a65d7d7b07f49df9ce90620b79d9a2d78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74019 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28soc/intel/xeon_sp: Use simple device function for setting PMAX_LOCKJonathan Zhang
Change to use simple device function for setting PMAX_LOCK because the Sapphire Rapids PCU device is not scanned during coreboot PCIe bus scan and would see "PCI: dev is NULL!" failure. Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400 Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28util/cbfstool: Add usage information about verbose outputMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ica512d21d1cef8ccffbc093016c7a3bfcf901b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73488 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-28cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOSMaximilian Brune
Currently ifdtool --validate will not correctly validate the FMAP against the IFD regions, since it will compare the IFD bios region with an FMAP region called SI_BIOS. It's probably a good idea to define default name for the BIOS FMAP region like we have for 'COREBOOT' or 'FMAP' FMAP region. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I55eddfb5641b3011d4525893604ccf87fa05a1e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28util/ifdtool: Add option to create FMAP templateMaximilian Brune
On systems that do not provide their own *.fmd (Flashmap) file, we fall back to a default flashmap file. That file however does not contain the blobs (ME, GBE ...), that are usually placed below the BIOS Flashmap. It can therefore easily happen that the placement of the blobs collides with the placement of the BIOS region (e.g. if CBFS_SIZE is big enough). The fmaptool can't catch that, since it does not know of the blobs placement. This patch basically maps the regions described in the IFD (Intel Firmware Descriptor) to the default Flashmap. Test: Build and see that build/fmap.fmd contains all blobs now (on intel systems that are supported by the ifdtool) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I82cb252fff456773af69943e188480a4998736fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-27soc/amd/stoneyridge/Kconfig: select SOC_AMD_COMMON_BLOCK_SVI2Felix Held
Stoneyridge uses the serial voltage ID 2 standard to tell the VRM on the board which voltage it wants, so select the SOC_AMD_COMMON_BLOCK_SVI2 Kconfig option to have the corresponding code to decode the raw SVI2 value into a voltage. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7d7031d9ad997a86c18d0e9e7af9a88ddf2d873c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-27mb/google/geralt: Set up open-drain ChromeOS pinsjason-ch chen
Set open-drain GPIOs for ChromeOS as input and bias-disable mode. After applying this patch, the voltage of these pins will become the expected value 1.8V (previously 1.0V), preventing wrong judgement of low/high. Reference document: MT8188G_GPIO_Formal_Application_Spec_V0.3 BUG=b:274058085 TEST=build pass Change-Id: I057716df6c59efb84fc395109db022b82ce528c4 Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73963 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27mb/google/skyrim: Add UPD usb3_port_force_gen1 for skyrimPatrick Huang
Add UPD usb3_port_force_gen1 for skyrim The default setting is set to disable Skyrim -> set default as disable BUG=b:273841155 BRANCH=skyrim TEST=Build, verify the setting will be applied on skyrim. Change-Id: Id53bed82a9fef93b574c3f30830555e02d7f4737 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27soc/amd/common/block/cpu/Makefile: group build targets by stageFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb6087dc44e76ab63bc6b462c3328c23d83ae018 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74009 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd/common/block/cpu/svi2: drop unneeded core_vid checkFelix Held
A core voltage ID larger than 0xff shouldn't happen, since SVI2's core VID is only 8 bit long. In order for making it more difficult to use this function in a wrong way that results in a very wrong voltage being returned, also return 0 for those invalid core VID values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95417c45db86cd2373879cdad8a07fb9eb8dfdda Reviewed-on: https://review.coreboot.org/c/coreboot/+/74000 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd/mendocino: Add UPD to support USB3 force to gen1 by portPatrick Huang
Add UPD usb3_port_force_gen1 to support USB3 port force to gen1 BUG=b:273841155 BRANCH=skyrim TEST=Build, verify USB3 port setting to gen1. Change-Id: Iaa476f56cf10588d7de2203deca4122958c00783 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27vc/amd/fsp/mendocino:Add fch_usb_3_port_force_gen1 tp AGESA FSP-M UPDPatrick Huang
To add fch_usb_3_port_force_gen1 parameter to force usb3 port to gen1 BUG=b:273841155 BRANCH=None TEST=Build Change-Id: I7560abb9a5fda6af3c2814f8b26c92925d8c17f4 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27soc/amd/mendocino: Add UPDs for DPTC current limitsPatrick Huang
Add UPD vrm_current_limit_mA, vrm_maximum_current_limit_mA, vrm_soc_current_limit_mA for DPTC. Make sure UPD parameterare are set to be aligned. BUG=b:245942343 BRANCH=none TEST=confirm the UPD parameters has been set correspondingly with the FSP UPD. Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73875 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27soc/amd/stoneyridge/include/msr: add pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs which will be used in future patches to generate the P state ACPI packages for the CPU objects. BKDG #55072 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I944c8598ba95a0333124655c61ef9eba8a7595c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73998 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd: factor out common get_pstate_core_power implementationFelix Held
Now that all get_pstate_core_power implementations in each SoC's acpi.c file is identical, factor it out into a common implementation. This implementation will also work for Stoneyridge which isn't using the common P state code yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iba3833024a5e3ca5a47ffb1c1afdbfd884313c96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73997 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd: introduce and use get_pstate_core_uvolts for SVI2 and SVI3Felix Held
Since SVI3 has the CPU voltage ID split into two parts, a serial voltage ID version specific function is needed to get the raw core VID value. This will allow making get_pstate_core_power common for all AMD CPUs in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71ca88c38b307558905a26cce8be1e8ffc5fbed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73996 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd: introduce and use get_uvolts_from_vid for SVI2 and SVI3Felix Held
Instead of implementing the conversion from the raw serial voltage ID value to the voltage in microvolts in every SoC, introduce the SOC_AMD_COMMON_BLOCK_SVI[2,3] Kconfig options for the SoC to select the correct version, implement get_uvolts_from_vid for both cases and only include the selected implementation in the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I344641217e6e4654fd281d434b88e346e0482f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73995 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27mb/google/brya/var/omnigul: Add WIFI SAR tableJamie Chen
Add WIFI SAR table for omnigul. BUG=b:273170023,b:273652516 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I2db057371754961503cfdc59f21c365fc82672c4 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73940 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-26drivers/spi/spi_flash.c: Prefer 'if' over '#if"Fred Reitberger
Change preprocessor #if to a regular if and let the compiler optimize away the unused branch. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7af747812a448064ac6b38686b8bd616a755932e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-26mb/google/geralt: Set orientation to LB_FB_ORIENTATION_BOTTOM_UPYidi Lin
Set orientation to LB_FB_ORIENTATION_BOTTOM_UP to align the volume up/down direction with menu up/down in FW screen. BUG=b:274749478 TEST=see FW screen in portrait mode. TEST=volume key behaves as expected Change-Id: If32859c4bf256c97147622ff04a17fc2ec80303d Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-26mb/google/brask/var/constitution: Add TcssAuxori for constitutionMorris Hsu
Enable SBU orientation handling by SoC for both USBC port2 and USBC port3. Constitution USBC port1 has retimer but USBC port2 and USBC port3 don't, they do not flip the data lines, hence we need to set bits for USBC ports. Change-Id: I4c5dfdba6c38c6e2f308b281ed316bb687ad8d8b Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-26mb/starlabs/*: Remove sleepstates.aslSean Rhodes
Remove the sleepstates.asl as it was written for SOCs pre-Skylake and not needed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I46fe934c2a50b3d61575f66f0881ab6754fe8dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-03-26mb/amd/birman/Kconfig: Select SPI_FLASH_FORCE_4_BYTE_ADDR_MODEFred Reitberger
Birman requires 4-byte addressing for flash. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id732129cfc14bb47e8f3d7f3de479815e040ea16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-26drivers/spi: Add SPI_FLASH_FORCE_4_BYTE_ADDR_MODEFred Reitberger
Add Kconfig option to force 4-byte addressing mode. Some platforms require the flash to stay in 4-byte addressing mode where it expects 4-byte addresses on regular commands. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2e41da2a78285c23c1c1d97eaf3969749812327b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-26mb/amd/birman: Move EC FW to FMAPFred Reitberger
Move EC FW from a CBFS file to an FMAP entry and rename the EC signature section to EC_SIG. An offset of (16M - 512K) was chosen to line up the EC FW before the RW_MRC_CACHE. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9b19d92043790b10acd20fbfdf394d5bd67b8295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-26soc/intel: Move USB PORTSC definition into IA common codeSubrata Banik
This patch moves USB Port Status and Control (PORTSC) Reg definition into IA common code to allow other SoC code to reuse it without redefining the same for each SoC. TEST=Able to build and boot google/taeko where USB wake is working. Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-25soc/intel/xeon_sp/chip_common.c: Probe all buses in attach_iio_stacks()Jonathan Zhang
For some Xeon-SP (such as SPR-SP), more buses should be probed. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-25soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP supportTim Chu
Add support for Intel SPR-SP to uncore_acpi.c. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-25mb/asrock/b75pro3-m: Remove cpu_fan_tach_src from CMOS layoutFabian Groffen
Commit 65c456227e1 (mb/asrock/b75pro3-m: Add CMOS layout/defaults and vbt.bin) introduced CMOS settings for selecting CPU_FAN{1,2}, but this code was never implemented. Remove the fake setting for it. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Ic2f4aa42f9cfd77defc2a11e16643690356bc26b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-25mb/google/rex: Use HI-556W for Proto 1 SKUsSubrata Banik
This patch drops the UFC sensor OV2740 (reused from the Brya chassis) support for Rex and added support for Rex specific UFC sensor HI-556W. BUG=b:269499723 TEST=Verified UFC is working on google/rex Proto 1. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b8ac08adec351a103ac1764d974db4881dc4d6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/70225 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-25soc/amd/common/include/cppc: remove cppc_config forward declarationFelix Held
The included acpi/acpigen.h provides the cppc_config struct and nothing in this header file is using the cppc_config struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia91fd4105e6872d812f595447783d02a0dd1568b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73993 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-25soc/amd/common/include/cppc: rename include guardFelix Held
When the code was made common in commit 8f7f4bf87a23 ("soc/amd/cezanne, common: factor out CPPC code to common AMD SoC code"), the include guard wasn't renamed accordingly, so do that now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9eefe2065fae31e97aa4e6710008a6f9712bed40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73992 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-24soc/amd/*/include/msr: add version number to SERIAL_VID_* define namesFelix Held
Picasso and Cezanne use the serial voltage ID 2 standard to communicate the CPU voltage to the voltage regulator module on the mainboard, while Mendocino, Phoenix and Glinda use the serial voltage ID 3 standard for this. Both standards encode the voltage in a different way, so add the serial VID version number to the defines to clarify for which version the define is. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8ddab8df27c86dc2c70a6dfb47908d9405d86240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73994 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-24soc/amd/mendocino: add and use missing cpu_vid_8 pstate_msr fieldFelix Held
Mendocino uses the SVI3 standard for CPU core voltage control which uses 9 data bits instead of the 8 in the SVI2 case and also calculates the actual voltages with a different formula. The Mendocino code uses the correct formula since commit 8d2bfbce23f6 ("soc/amd/sabrina/acpi: Correct VID decoding on Sabrina"), but the MSR definition in the PPR hasn't been updated to show the additional bit. The definition of the register that is mirrored by these MSRs descries this 9th CPU voltage ID bit though. Since this bit is expected to be zero, this shouldn't cause a change in behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I05acd239300836a34e40cd3f31ea819b79766e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73969 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-24mb/prodrive/atlas: Configure some FSP settingsAngel Pons
Program some FSP settings as requested by Prodrive. Change-Id: I04548e5eddc8a6be3a03b5dd9062470b4ef85adb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24mb/prodrive/atlas: Implement initial VPD supportAngel Pons
Atlas stores VPD (Vital Product Data) in an I2C EEPROM, which is only connected to the EC. In order for the host (x86) to be able to access the VPD, the EC reads the EEPROM contents into a buffer in EC RAM and provides the host with read-only access to this EC RAM buffer through EMI (Embedded Memory Interface) 0. The VPD layout is designed to be extensible yet backwards compatible. The code in coreboot uses the revision field to know which fields are valid, and will populate the rest with fallback values. Use the serial number and part number in VPD to populate SMBIOS tables. Change-Id: I2d3d70fee22548daa73ef98af56c98e950dc5e9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24mb/prodrive/atlas: Add support to read from EC EMIAngel Pons
Implement initial support for EMI (Embedded Memory Interface), which Microchip describes as "a standard run-time mechanism for the system host to communicate with the Embedded Controller (EC) and other logical components". EMI allows the host to access regions of EC memory without requiring any assistance from the EC. For now, Atlas only uses EMI 0. This change enables EMI 0, subsequent commits will read data from it. Change-Id: Ia899ae71e97f9fc259397dfb5fb84ca06545f5d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24soc/intel/xeon_sp/smihandler.c: enable support for spr-spTim Chu
For SPR-SP, the SMM_FEATURE_CONTROL register is in UBOX_URACU_FUNC instead of UBOX_DEV_PMON. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ide46c5f9cdf65b7e05552449b08ad4d7246664cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-24amdfwtool: Clean up table buffers before combo loopZheng Bao
Keep clean copies of PSP and BIOS table. Refresh the working tables before they are filled with file names and other information at each iteration. Change-Id: Ie8339a4d66c38e02180cbf99e13914bfff66dc0f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Add missing help information for --combo-config1Zheng Bao
Change-Id: I6b69965991daadaf8b4148b06d0715b087021c9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Call wrapper funtion to write fileZheng Bao
Don't call system call directly. Change-Id: I6da31723bc2bfc1197fc31962053671c84ccc397 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Move some funtions to other categorized source filesZheng Bao
To reduce the size of amdfwtool.c which is already too big. Change-Id: Ib80eeb42f59a3dda04402b2feaadc1d178ed989e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24nb/intel/i440bx: Die with standard POST code on fatal conditionsKeith Hui
When encountering really incompatible memory configurations, post a standard POST_RAM_FAILURE code when dying. Gone are the "HALT" messages that no longer serve any good purpose, instead fatal messages are edited to always end with "!" to make them stand out even with loglevel prefix off. Change-Id: Ie1b9e5a0415e4c64b1f4e935689263f62db012b2 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-24soc/amd/*/include/msr: drop _LO part from PSTATE definition namesFelix Held
The _LO part in the definition names is a leftover from before moving to the pstate_msr union access to the bitfield elements where it still mattered if a bit was in the lower of higher half of the MSR. With the mask-and-shift access to the two parts of the MSR being gone, the _LO part in the name isn't useful any more and possibly a bit misleading, so drop that part. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib43c71e946388c944ecf40659d4c12ca02a27a5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73927 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-24soc/amd: pass pstate_msr union to get_pstate_core_[freq,power]Felix Held
Since we already have and use the pstate_msr union in get_pstate_info, also pass it directly to the get_pstate_core_freq and get_pstate_core_power function calls avoids having to sort-of convert the msr_t type parameter in the implementations of those two functions. In amdblocks/cpu.h a forward declaration of the pstate_msr union is used since soc/msr.h doesn't exist in the two pre-Zen SoCs that also include amdblocks/cpu.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I112030a15211587ccdc949807d1a1d552fe662b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73926 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-24mb/google/geralt: Read LCM ID from ADC channels 4 and 5Yidi Lin
The SKU ID is not really used on Geralt. Both ADC channels 4 and 5 will be used for LCM ID on derived projects. For Geralt reference board, only PANEL_ID_LOW_CHANNEL is valid. BRANCH=none BUG=b:247415660 TEST=boot Geralt proto0 and see FW screen in DEV mode. Change-Id: I77a3caadc1b0be5bf39dd2cf73ea1df88f9a09ea Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73874 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-24cpu/intel: Remove redefined SAPPHIRERAPIDS_SP CPUID to fix build errorJohnny Lin
This reverts pieces of commit 08135332dd "soc/intel/xeon_sp: Report platform cpu info" Reason for revert: Due to duplicated definitions this breaks the tree. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I7bcffe99e4f049e38d9a13c82d38464c64250ee1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74002 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-23soc/amd/common/block/acpi/cpu_power_state: use pstate_msr unionFelix Held
Use the pstate_msr union in get_pstate_info to check if the P state enable bit is set. Also drop the now unused PSTATE_DEF_HI_ENABLE_SHIFT and PSTATE_DEF_HI_ENABLE_MASK definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I79119e09af79a4bb680a18e93b4a61a049f0080e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-23soc/amd/glinda: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs which will be implemented in a following patch. PPR #57254 Rev 1.52 was used as a reference. This patch adds and uses the cpu_vid_8 bit which is the 9th bit of the voltage ID specified in the SVI3 spec. The way the CPU frequency is encoded in the PSTATE MSR has changed compared to Phoenix, so also update the comment in the SoC's Kconfig file that the selected SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H is likely incompatible which will be addressed in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d1878ce4d9bc62ac597e6f71ef9630491628698 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-23soc/amd/phoenix: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference as well as the reference code. This patch also adds and uses the cpu_vid_8 bit which is the 9th bit of the voltage ID specified in the SVI3 spec. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia024d32ae75cf2ffbc2a2e86a8b3af3dc6cbad61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-23mb/prodrive/atlas: Add workaround for CLKREQ pinsMaximilian Brune
Intel Client PCIe* controller expects each device should drive the SRCCLKREQ#. If the GPIO is set to native mode for a device, which does not support SRCCLKREQ#, then during RTD3 exit link would not be established. Because controller samples the SRCCLKREQ# before detecting the device and break L1 as the system might enter L1SS as controller detects SRCCLKREQ# as de-asserted. As a workaround the Pins must not be configured in Native Mode (CLKREQ native function). Therefore here they are not configured at all. source: 689882 (intel document ID) So apparently hardware doesn't sample SRCCLKREQ Pin if it's not configured as such. That workaround suggestion however also brought a patch to FSP, which in turn causes the same bug (even if SRCLKREQ are not configured). Usually in order to make use of root port power saving features (e.g. clock gating), the Root port must either be disabled or a CLKREQ Pin must be configured. The patch however removed that check before enabling power management for the rootport. Workaround (until FSP is fixed): pretend to FSP that the rootports have a CLKREQ Pin attached, by supplying them in the FSP UPDs. That will cause FSP to configure the CLKREQ Pin and enable power management for said rootport, but it will not crash on L1 entry/exit. That has been done on the Atlas board (as workaround) for a short period of time (before applying FSP Fix) like this: // RP 5 (the rootport you want to fix) - memupd->FspmConfig.PcieClkSrcUsage[2] = 4; // e.g. choose a clkreq pin that is not routed out - memupd->FspmConfig.PcieClkSrcClkReq[2] = 0; Furthermore disable CpuPcieRpClockReqMsgEnable FSP-M options to prevent the same issue, but for CPU root ports. If not done the following will happen in coreboot: [DEBUG] PCI: 00:06.2 scanning... [SPEW ] do_pci_scan_bridge for PCI: 00:06.2 [DEBUG] PCI: pci_scan_bus for bus 02 [DEBUG] PCI: 02:00.0 [1344/5410] enabled [INFO ] PCIe: Common Clock Configuration already enabled [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] ASPM: Enabled L1 [EMERG] CPU Index 9 - APIC 32 Unexpected Exception:18 @ 10:76aeb93f - Halting [EMERG] Code: 0 eflags: 00000046 cr2: 00000000 [EMERG] eax: 00000000 ebx: 00000009 ecx: 00000000 edx: 00000000 [EMERG] edi: 00000009 esi: 76b218c4 ebp: 00000000 esp: 76b29100 [EMERG] 0x76aeb8f8: c4 2c 5b 5e 5f 5d c3 56 [EMERG] 0x76aeb900: 53 83 ec 14 65 a1 00 00 This patch is only a workaround for the issue and it will be reverted as soon as FSP is fixed. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I324bc6ab158d4b3b5ae9d3bade21076b44bc8892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-23soc/intel/xeon_sp: Report platform cpu infoNaresh Solanki
Add platform cpu info for known microcode, print cpuid & processor branding string. This will print as in the following example: CPU: Intel(R) Xeon(R) Platinum 8468H CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130 CPU: AES supported, TXT supported, VT supported Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-23mb/asrock/b75m-itx: Set HDA pin configuration like vendor BIOSKevin Keijzer
While doing the initial port of this board, hda_verb.c was mainly put together by guesswork and borrowing the pinouts from similar boards. While it was mostly correct, not everything was tested properly. This change takes the values of vendor BIOS version P1.80, obtained by running `cat /sys/class/sound/hwC0D0/init_pin_configs` while booted from the vendor firmware. 7.1 channel audio and front panel audio are now also tested. Change-Id: I60b0f55c203f42b220f13cf943912f7428476792 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73935 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fabian Groffen <grobian@gentoo.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-23mb/hp/snb_ivb_laptops: Add HP EliteBook 2170p as 2570p variantBill XIE
Most of the code is taken from 2570p, adjusted with autoport, SuperIO from 8470p and inteltool, GPIO config from inteltool via autoport. The laptop works well under coreboot with SeaBIOS 1.16.1 payload, running Debian GNU/Linux with kernel 6.1.15. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I854104516d5b6fbd78ee2989197000a7dbb85136 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73856 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23mb/asrock/b75m-itx: Move subsystemid from NIC to PCIe root port 4Kevin Keijzer
As a follow-up to commit 1a591d0c4460 (mb/asrock/b75m-itx: Make NIC a child device below PCIe port 4), this change corrects the subsystemid being incorrectly applied to the Realtek NIC instead of the PCIe root port. Change-Id: Ib6fb8bf808132c008846d8ca9acde0eef277765c Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23mb/asrock/b75m-itx: Remove cpu_fan_tach_src from CMOS layoutKevin Keijzer
This board inherited cmos.default and cmos.layout from asrock/h77pro4-m, which has two CPU fan headers and a CMOS option to select which one will provide the tachometer source. However, the code for this was never implemented. Moreover, this board only has one CPU fan header, rendering the option useless. This change removes the option from cmos.layout and cmos.default. Change-Id: Ib4580e243781e2340af2cefb825f26ee896c2bd3 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73931 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23soc/intel/xeon_sp: Fix PCH IOAPIC IDPatrick Rudolph
FSP may program a different ID under certain circumstances. Read IOAPIC ID from hardware instead of using some define that might not reflect how hardware is configured. Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23nb/intel/snb: Abolish mainboard_should_reset_usb()Keith Hui
Of the 13 mainboards that implement mainboard_should_reset_usb() hook, all but one do the same: Stop MRC from resetting USB when resuming from S3 suspend. This hook turns out is only here to facilitate a USB reset workaround on samsung/stumpy for an old ChromeOS kernel which is no longer needed. Drop the workaround, the hook, and headers no longer used. roda/rv11/early_init.c is left with no useful code after this patch, so drop it entirely from both bootblock and romstage. Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-23soc/intel/cmn/cse: Make heci_(send|receive) public functionsJeremy Compostella
Having these two functions public allow "asynchronous" HECI command implementation. Typically, these function can be use to implement an asynchronous End-Of-Post. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Successful compilation for brya0 Change-Id: I7d029bb9af4b53f219018e459d17df9c1bd33fc1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-23soc/amd/mendocino: Remove GPP bridge to Bus BMartin Roth
The internal GPP bridge to bus B is not used on MDN, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4f95afd192c5b799b7a3e12650476b7933cdd118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-23soc/intel/elkhartlake: Define DIMM_SPD_SIZE in SoC KconfigMichał Żygowski
The default SPD size is set to 256 bytes, instead of 512 for LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused the SMBus libraries to read only the lower half of the DIMM SPD on protectli/vault_ehl. The lower half of the SPD passed to FSP causes a bug in DIMM change detection, which relies on the CRC of the manufacturer bytes in the upper half of the SPD (CRC of zero bytes always gives zero so no change was assumed). Setting the DIMM SPD size to 512 fixes it. Setting the SPD size in SoC will also avoid such problems in the future Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing the correct default of 512 bytes is an obvious thing to do. TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see FSP is retraining the memory instead of doing the fastboot with old DIMM data. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23mb/google/brya/var/taeko: Correct comments to prevent confusionJoey Peng
The PCIE RP 9 on taeko is for eMMC. Correct the comments to prevent confusion. BUG=b:271003060 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib49942b682d1817af9e8b4b61044aa170e18fea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 17:09:45 +0000