diff options
| author | Joey Peng <joey.peng@lcfc.corp-partner.google.com> | 2023-03-22 11:21:24 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-03-23 08:30:40 +0000 |
| commit | 496e4e95c4cba9f5414cd8137fa151a9b3fe0b21 (patch) | |
| tree | 0ec45e311b1f221ad6fe698c84c2b39c24f5a9a5 | |
| parent | 30a011417fb227d8e1e78a6a47abd9ea332c00c7 (diff) | |
mb/google/brya/var/taeko: Correct comments to prevent confusion
The PCIE RP 9 on taeko is for eMMC.
Correct the comments to prevent confusion.
BUG=b:271003060
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib49942b682d1817af9e8b4b61044aa170e18fea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/taeko/overridetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 00d7e69b03..cdfd2ff49d 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -532,7 +532,7 @@ chip soc/intel/alderlake end end device ref pcie_rp9 on - # Enable NVMe PCIE 9 using clk 0 + # Enable PCIE 9 using clk 0 for eMMC register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 0, .clk_req = 0, |