diff options
| author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-23 16:33:03 -0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-28 13:28:46 +0000 |
| commit | ffc5a1ce301b2feae6f5ee7cc6480dce18db9b81 (patch) | |
| tree | d9b72a3fc02413c6b755d4e66f02c6075a5542d2 | |
| parent | 60c6a5a6fe9ead018f4ed4ba20c0cbcebd5824e1 (diff) | |
soc/intel/xeon_sp: Use simple device function for setting PMAX_LOCK
Change to use simple device function for setting PMAX_LOCK because
the Sapphire Rapids PCU device is not scanned during coreboot PCIe
bus scan and would see "PCI: dev is NULL!" failure.
Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
| -rw-r--r-- | src/soc/intel/xeon_sp/util.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index c4a10f9a9c..7524e52900 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -320,7 +320,9 @@ static void set_bios_init_completion_for_package(uint32_t socket) die("BIOS RESET CPL3 timed out.\n"); /* Set PMAX_LOCK - must be set before RESET CPL4 */ - pci_or_config32(PCU_DEV_CR0(bus), PCU_CR0_PMAX, PMAX_LOCK); + data = pci_s_read_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX); + data |= PMAX_LOCK; + pci_s_write_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX, data); /* update RST_CPL4, PCODE_INIT_DONE4 */ timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, |