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2022-05-20libpayload/pci: Add pci_map_bus function for MediaTek platformJianjun Wang
Add 'pci_map_bus' function and PCIE_MEDIATEK config for MediaTek platform. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-20libpayload/pci: Add support for bus mappingJianjun Wang
Move the common APIs to pci_ops.c and IO based operations to pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-20soc/mediatek: Fill coreboot table with PCIe infoJianjun Wang
In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot table with PCIe info. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-19mb/google/brya/var/kinox: Remove stop pin declaration for LANDtrain Hsu
Remove the stop pin declaration for LAN. Confirmed with LAN vendor, 8111K do not need to implement stop pin. It caused S0ix fail. BUG=b:232327947 TEST=Build and suspend_stress_test -c 5 pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I9bdaa28cd879c1ea7de2de8afb25761df39bcfc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-19coreboot_tables: Add PCIe info to coreboot tableJianjun Wang
Add 'lb_fill_pcie' function to pass PCIe information from coreboot to libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the __weak function. ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller for payloads to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2022-05-19arch/x86/car.ld: Add a Kconfig param to flag AGESA brokennessArthur Heymans
AGESA has a lot of code in the .data section (initialized data). However there is no such section in CAR stages as the code runs in XIP mode and CAR is too small to contain the data section. When the linker can not match code to a section it will just append it, which is why AGESA worked at all. Follow-up patches will attempt to fix AGESA and set Kconfig parameter to 'n'. After all AGESA sources have been fixed, this can be removed. Change-Id: I311ee17e3c0bd283692194fcee63af4449583d74 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-05-19mb/google/nissa: Rework LTE GPIO configurationReka Norman
Currently, the LTE pins are enabled in gpio.c, then disabled in fw_config.c if LTE is not present. However, since there's a short delay between mainboard_init() and fw_config_handle(), this means that when LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR sensor) will be floating for a short period of time. Rework the GPIO config so that the LTE pins are disabled in the baseboard, then enabled in fw_config.c for variants using LTE. However, this doesn't work for WWAN_EN and WWAN_RST_L since they need to be enabled in bootblock. So these are instead enabled in the variant gpio.c, then disabled in fw_config.c if LTE is not present. BUG=None TEST=LTE still works on nivviks Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-19mb/google/dedede/beadrix: Update PCIe and SATA pins for Realtek RTL8822CE ↵Teddy Shih
suspend To make sure Realtek RTL8822CE suspend stress test smoothly, we remove 1c.7 as wireless LAN (WLAN) connects the signal PCIE_4 and it will map to 1c.7. refer to Intel Simon comment (https://partnerissuetracker.corp.google.com/issues/230386474#comment12), as well as, remove redundant 17.0 and 1c.6 that both are described by baseboard/devicetree.cb BRANCH=dedede BUG=b:230386474 TEST=on beadrix, verified by Realtek RTL8822CE can run suspend stress test properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ib418eed57f07afaa6b397b42a057808eab142f7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-05-19soc/intel/common/block/smbus: Deduplicate some codeAngel Pons
Reuse existing SMBus code from southbridge/intel/common/smbus_ops.h. Change-Id: Iea4f6886bb49590f7f96abbfbe631ac9d4dda902 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64432 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-19drivers/intel/fsp2_0: Avoid hardcoding `log_level` for FSP debug handlerSubrata Banik
This patch fixes a potential corner case scenario where the value of CONFIG_DEFAULT_CONSOLE_LOGLEVEL is less than `BIOS_SPEW` hence, coreboot is unable to redirect FSP serial messages over UART. Rather than passing hard coded `BIOS_SPEW` for the FSP debug handler, this patch now calls get_log_level() function to pass the supported log level while printing FSP serial msg. BUG=b:225544587 TEST=Able to build and boot taeko. Also, able to see FSP debug log with CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8a18101f5c3004252205387bde28590c72e05b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64460 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-18mb/google/brya/var/crota: Add reset and enable delay time for rtd3-coldTerry Chen
This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin delay of 50ms and add delay of 20ms to meet the sequence on various eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:231291431 TEST=USE="project_crota" emerge-brya coreboot chromeos-bootimage Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Id9bed46e801602f3f327753053ec6a1ceb0656e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-18soc/intel/elkhartlake: Skip FSP Notify APIsLean Sheng Tan
Follow this commit 95986169f (soc/intel/alderlake: Skip FSP Notify APIs) to skip FSP Notify APIs. Elkhart Lake SoC deselects Kconfigs as below: - USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE to skip FSP notify APIs (Ready to boot and End of Firmware) and make use of native coreboot driver to perform SoC recommended operations prior booting to payload/OS. When deselecting these Kconfigs, cse_final_ready_to_boot() and cse_final_end_of_firmware() in the common cse driver will be used instead as required operations to perform prior to booting to OS. Check out this CL for further info: commit 90e318bba (soc/intel/common/cse: Add `finalize` operation for CSE) Additionally, create a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again config. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-18soc/intel/ehl/tsn_gbe.c: Reduce `void *` castsAngel Pons
Remove two redundant `void *` casts in `clrsetbits32()` calls. In addition, preemptively retype the `io_mem_base` variable in order to avoid having to add casts in future commits. Change-Id: Iae9c8189a6f8cd29181c52c2241789c6d392d77b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-18soc/intel/alderlake: Add support enable external V1P05/Vnn railsV Sowmya
This patch adds the support to enable the external V1P05/Vnn rails in S0 state via devicetree. BUG=b:223102016 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-18soc/intel/alderlake: Update the VccIn Aux Imon IccMaxV Sowmya
This patch updates the VccIn Aux Imon IccMax for ADL-N to SOC SKU specific value of 27A. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified that VccIn Aux Imon IccMax value is set to 27mA. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: If09cd1112fac9b30ff04c45aa5a6062c2513c715 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-18soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya
This patch configures the SKU specific power delivery parameters for the VR domains for ADL-N. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 081 | IA | 4.7 | 4.7 | 53 | 22 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 22 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 081(7W) | IA | 5.0 | 5.0 | 37 | 14 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 14 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | + Pentium +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 12 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | + Celeron +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 26 | 12 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 021(6W) | IA | 5.0 | 5.0 | 27 | 10 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 23 | 10 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ Kit: 646929 - ADL N Platform Design Guide -> Power_Map_Rev1p0 BUG=b:223102016 TEST=Boot and verify the UPD values are configured properly for ADL-N SKU's. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I3d6ae20323d3e859f52228822d4cbad143921a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-18mb/google/nissa: Change EC wake interrupt to IRQEric Lai
EC wake event doesn't work. Nissa has a separate EC wake pin. SCI only is not handled by EC, so we need to set dual route to wake the system. BUG=b:229142661 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ide1f4a2494bb0a64b11ab4c5135fc43d2a635f74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-18intel/common/block: Provide RAPL and min clock ratio switches in commonUwe Poeche
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-18arch/x86: Make sure bootblock gets buildtestedArthur Heymans
Now that the bootblock isn't added to cbfs anymore, on some targets it's only conditionally build. One example would be Intel APL where it only gets build when stitched into an IFWI. This is always done when compiling for real targets but not by the CI builder. This adds a dummy target to make sure the bootblock always gets buildtested. Change-Id: I60601e01a2c370b5c21493b71d51f495bb42f41d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-17amd/agesa/heapmanager.c: Avoid pragma pack on the rest of the fileArthur Heymans
AGESA.h has a '#pragma pack' nested somewhere. The pack pragma packs all structs which is not what is expected in the structs inside the headers included below AGESA.h. Change-Id: Ia70f68ea0ece7c097a37517206d75b71d695561f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-17mainboard/**/devicetree.cb: Fix typoAngel Pons
repalcement ---> replacement Change-Id: I486170e89f75fa7c01c7322bb8db783fd4f61931 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64404 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17soc/intel/elkhartlake/chip.h: Drop unused membersAngel Pons
Remove devicetree options that aren't used anywhere in the code. Change-Id: I7eace61079e14423325332d277fdda4f986fd133 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64403 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17soc/intel/elkhartlake: Enable SMBus depending on dev stateAngel Pons
Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's state in the devicetree. This avoids having to manually make sure the SMBus PCI device and the `SmbusEnable` setting are in sync. Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17lib/Makefile.inc: Correct filename to master_header_pointer.cReka Norman
Builds are failing sporadically with: src/lib/master_header_pointer.c:5:10: fatal error: fmap_config.h: No such file or directory 5 | #include <fmap_config.h> | ^~~~~~~~~~~~~~~ Correct the filename in the Makefile from header_pointer.c to master_header_pointer.c so that there's a dependency from master_header_pointer.c to fmap_config.h. Change-Id: I41bcb2a21fdbc48f09d5b6be3e211ca56607d849 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64431 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17mb/google/brya/var/mithrax: update overridetree and KconfigJohn Su
1. Update override devicetree based on schematics. 2. Update Kconfig based on schematics. BUG=b:229191897 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ia28ae16f609fda6d90558e69b2d41139dbe533fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-17mb/google/brya/var/mithrax: Generate RAM ID and SPD fileJohn Su
Add the support RAM parts for mithrax. Here is the ram part number list: DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) MT53E1G32D2NP-046 WT:B 1 (0001) BUG=b:229191897 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I2d19721a44f0176365a81da30d2f49b68a14df7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-17mb/google/brya/var/mithrax: update gpio settingsJohn Su
Configure GPIOs according to schematics BUG=b:229191897 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I31a1e02b2fa3d2075efbf488cd611b6c5a88500f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-17soc/amd/block/psp/psp_gen2: move SPL fusing earlier to BS_PAYLOAD_LOADFelix Held
The psp_notify_boot_done call is done at the entry of BS_PAYLOAD_BOOT, so it's not guaranteed that the psp_set_spl_fuse call is done before the psp_notify_boot_done call. Moving the psp_set_spl_fuse call makes sure that it's done before the psp_notify_boot_done call. This also brings the psp_set_spl_fuse call in line with the enable_secure_boot call that sends the PSB fusing command to the PSP. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id76b462608c3d788cd90e73a64d18c8e8b89dbfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-17soc/intel/skylake: Hook up FSP hyper-threading setting to option APIFelix Singer
Hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard kontron/bsl6, since it is obsolete now. Change-Id: I1023d1b94acb63f30455c56b394b68059deaaa16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-17mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridgeMario Scheithauer
On this mainboard there are legacy PCI devices connected behind a PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This patch disables the unused PCI clock outputs on the XIO2001 bridge. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17arch/x86/ebda.c: Move setting up ebda to a BS hookArthur Heymans
device.c should not hold arch specific code. Change-Id: I9dfdb905a83916c0e9d298e1c38da89f6bc5e038 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-17mb/google/brya/var/kinox: Set memory SMBus addresses to 0x52, 0x50Dtrain Hsu
Follow the Kinox_schematic_R01_20220418.pdf to set memory SMBus addresses to 0x52, 0x50. BUG=b:231398371 TEST=Build and boot to OS with either 1 or 2 DIMM slots populated. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I32bb4f62a6b8a485ac757a60f5d16adb69109e2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-173rdparty/intel-microcode: Update submodule to recent main branchFelix Singer
Updating from: 115c3e4 microcode-20220207 Release Updating to: 72bdc2c Merge pull request #59 from esyr-rh/microcode-20220510-releasenote-fixes This brings in 4 new commits: * 72bdc2c Merge pull request #59 from esyr-rh/microcode-20220510-releasenote-fixes * 6ff5aa2 releasenote.md: changes summary fixes for microcode-20220510 * 9255555 microcode-20220510 Release * 686ce06 microcode-20220419 Release Change-Id: Ia8c67a4c6732c05f6dbcd4b9d7d344add2357dba Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-17mb/google/nissa: add RO_GSCVD section to WP_ROKangheui Won
This area is used for storing AP RO verification information. BRANCH=none BUG=b:227801913 TEST=build and boot nivviks Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: If5c03aca56e659d61c31613b284a55d0eba0d843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16rules.h: Use more consistent namingArthur Heymans
Use 'ENV' consistently and drop the redundant 'STAGE' in the naming. Change-Id: I51f2a7e70eefad12aa214e92f23e5fd2edf46698 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16Allow trailing whitespaces in .md filesMaximilian Brune
Two trailing whitesspaces have an actual meaning in Markdown files (a new line). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16util/testing: Remove amdfwread from makefileRobert Zieba
amdfwread was added to the testing makefile but ended up not becoming a separate tool. This commit removes it from the makefile so that `make distclean` works again. Fixes: 29bc79fddb62c30caa33474ac773ae6a6ec1c4f0 ("util/amdfwtool: Add amdfwread utility") TEST=Ran `make distclean` Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I2c8b920bc69d6c20558a28515c52a1e9cecebe27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64348 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/amd/cezanne/fsp_m_params: fix modification of constantFred Reitberger
mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is constant. Changing a constant is undefined behavior, so create a local static instance of usb_phy_config that can be modified safely. Change-Id: If9b76b869a5b0581f979432ce57cc40f1c253880 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-16soc/amd/cezanne/fsp_m_params: add defines for FSP USB struct versionFelix Held
Add and use defines instead of magic values in fsp_m_params.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64126 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/amd/cezanne/fsp_m_params: don't hard-code USB PHY config table sizeFelix Held
Use sizeof instead of having a hard-coded struct length. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85dc2fce11d9a670b2037d8a6a694177cfaa2177 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16mb/siemens/mc_ehl2: Enable TSN GbE driverMario Scheithauer
This variant uses all three EHL Ethernet GbE-TSN Controller so enable the TSN GbE driver in order to set the needed MAC addresses. The required function to retrieve a valid MAC address was already implement in the common mainboard.c for mc_ehl. TEST: - Boot mc_ehl2 into Linux and check MAC addr via 'ip a' Change-Id: Ia052c44feb606f9e1d31d047f2acc67e3226a895 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16soc/intel/elkhartlake: Provide ability to update TSN GbE MAC addressesMario Scheithauer
This patch provides the functionality to change the TSN GbE MAC addresses. Prerequisite for this is a mainboard specific function that returns a matching MAC address. A test was performed with the next patch in the series, which enables the TSN GbE driver for mc_ehl2 mainboard. Change-Id: I2303a64cfd09fa02734ca9452d26591af2a76221 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/siemens/mc_ehl2: Set PCH TSN link speed to 1 Gbps in devicetreeMario Scheithauer
TSN runs in SGMII mode on this mainboard. This requires setting the link speed to 1 Gbps. Change-Id: I9f1da971b4de5671d6d38be6dbc50edbbe20d157 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetreeMario Scheithauer
This mainboard uses all three internal Ethernet GbE-TSN controllers. Two of them are initialized by the Programmable Services Engine (PSE). This patch enables the Serial Gigabit Media Independent Interface (SGMII) mode for GbE PSE0 and GbE PSE1. By setting PCH PSE DMA pins to host owned, the IO is under control of the IA processor cores through system software. TEST: - Boot mc_ehl2 into Linux and check inet addr via 'ip a' Change-Id: I74e660548b2c44d5dbdb6023d5a36cfdd7e96f43 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16soc/intel/elkhartlake: Implement TSN GbE driverMario Scheithauer
To be able to make EHL Ethernet GbE-TSN Controller configurable, a driver is required. Functionality comes in following patches. Change-Id: I7522914c56b74486bb088280d2686acf7027d1d3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/google/brask/variants/moli: remove DB_OPT from overridetreeRaihow Shi
Both option-HDMI and option-DP use the same setting of vbt, and ABSENT is just physically remove option board from motherboard, so it just need one vbt, and it don't need the fw_config to decide which vbt will be return. BUG=b:231769131 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1f8cdcbc05ed3bc689d29261e4fd4d700326dce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/brask/variants/moli: return the default VBTRaihow Shi
Both option-HDMI and option-DP use the same setting of vbt, and ABSENT is physically remove option board from motherboard, so set default vbt has option-DP setting and only return it. BUG=b:231769131 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I440143dabcf04c103f2a4420a7e4afb8ec12ec1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16drivers/wifi/generic: Add new device IDBora Guvendik
New device id 0x51f1 is added. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I695309d529a117bad68fc89a7f136e69cecb95d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-16src/driver/intel/mipi_camera: Update ACPI entry to provide silicon infoBora Guvendik
CPUID_RAPTORLAKE_P_J0 is ES. Add it to generate is_es = 1 in ACPI Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib8d57f7fb0b3d15bc4bcdeae47bfbdde17e13118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-16soc/intel: Add Raptor Lake device IDsBora Guvendik
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2022-05-16superio/nuvoton/nct6687d: Add early support for NCT6687DMichał Żygowski
Based on the public datasheet of NCT6686 which should be similar to NCT6687D. TEST=Enable serial for debugging on MSI PRO Z690-A WIFI DDR4 and see coreboot console on the debug port Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0e8744b5958af196de3de63de31852029d81436e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16soc/intel/common: Implement IOC driverWonkyu Kim
Starting with Meteor Lake SoC, the PCR/DMI interface to program GPMR is replaced with IOC (I/O Cache), hence, this patch implements IOC driver to support that migration. Reference: 643504 MTL FAS section 7.5.2 TEST=Build and boot to OS for TGL RVP and MTL PSS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63198 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16acpi, arch/x86/smp/mpspec,soc/amd/common: Move MP_IRQ_ flags into acpi.hRaul E Rangel
The MP_IRQ flags can be used in the MP table and the ACPI MADT table. Move them into acpi.h to avoid pulling in the full mpspec.h which is only available on x86. BUG=b:218874489, b:160595155 TEST=Build Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f1091b7629a6446fa399720b0270556a926401a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63845 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/intel/cmn/spi: Separate fast SPI device from generic SPI driverWerner Zeh
The fast SPI controller (usually handling the boot NOR flash) is a different controller type than the generic SPI controllers as it provides access to the boot flash and usually is not used for generic SPI slave connections. Though there is common code for the fast SPI controller it currently do not uses the PCI driver structure. This patch adds the PCI driver envelope to the fast SPI driver and moves Apollo Lake as the first platform to this driver. Change-Id: I31bf39ec1c622db887dec9ca8623a7f282402849 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16soc/amd/common/block/psp: Add platform secure boot supportRitul Guru
Add Platform Secure Boot (PSB) enablement via the PSP if it is not already enabled. Upon receiving psb command, PSP will program PSB fuses as long as BIOS signing key token is valid. Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is only available with NDA customers. Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-16mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfigFelix Held
Use the existing definitions from FspUsb.h instead of magic values for the ComboPhyStaticConfig settings in the mainboard's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16arch/x86/postcar_loader.c: Change prepare_and_run_postcar signatureArthur Heymans
The postcar frame can now be a local variable to that function. Change-Id: I873298970fff76b9ee1cae7da156613eb557ffbc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16arch/x86/postcar_loader.c: Reduce the scope of functionsArthur Heymans
Some functions are only called locally. Change-Id: I96a4e40a225536f62abb2a15c55d333b8604e8cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16drivers/amd/agesa: Use prepare_and_run_postcarArthur Heymans
This removes some of the postcar setup boilerplate. Change-Id: I4f8f92b88ac16dd70ff4878dfc14e676386d4703 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-05-16soc/amd/stoneyridge: Use common prepare_and_run_postcarArthur Heymans
This reduces boilerplate postcar frame setup. Change-Id: I8e258113c90ee49864ceddf36ea296ba6f83afe4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16arch/x86/postcar: Set up postcar MTRR in C codeArthur Heymans
Setting up postcar MTRRs is done when invd is already called so there is no reason to do this in assembly anymore. This also drops the custom code for Quark to set up MTRRs. TESTED on foxconn/g41m and hermes/prodrive that MTRR are properly set in postcar & ramstage. Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54299 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16util/inteltool: Add support for Gemini LakeSean Rhodes
Tested on: * StarLite Mk III (N5000) * StarLite Mk IV (N5030) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16google/cyan: Clean up write_protect_state()Kyösti Mälkki
The commentary was wrong, write_protect_state() is only called in ramstage at the moment, and only if MRC_SETTINGS_PROTECT is selected. Implementation of get_gpio() eventually does the MMIO read, so BOARD_GOOGLE_CYAN was not a special case. Change-Id: I96ca871110bcf2fc1485bd042ed137d51b822a20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16src/vendorcode/cavium: Fix guard in bdk-require.hDavid Hendricks
Change-Id: I5d4ac11d0c9501dd3a753f8f29581552c484ff59 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16libpayload: Fix guards in include/{arm,arm64,x86}/arch/barrier.hDavid Hendricks
Change-Id: Ib4897c4f5837f7f3173d5062eecb893adbe36964 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16drivers/ipmi: Fix header guardDavid Hendricks
Change-Id: Ic1f33ce883443da1c68627e4c1db10871deecd0d Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64364 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/intel/*: Fix up header guardsArthur Heymans
Change-Id: If9ae375629c8af3d32b4c5493b5d63203e8847aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16mb/google/brya: Consistently put void before __weak attributeTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic59cccdf0fb88fc71a440170ee40b73dd8736a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16util/lint/lint-stable-019: Update grep '\s' to [[:blank:]]Martin Roth
For some reason, the '\s' syntax is causing an error for me under freebsd. It's entirely possible that I'm doing something wrong, but this change should be fine regardless. Freebsd's grep, GNU grep, and git grep all handle posix regex classes, so this change should be transparent. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I489ec13b4ea2e9c17692888e42b8741763b1a2c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16soc/intel/common: Consistently use smbus 7-bit address log formatKane Chen
The "No memory dimm at address" line in get_spd_sn and get_spd fucntion have different format of SPD address. get_spd_sn shows a 8-bit address format but get_spd shows a 7-bit address format when there is no DIMM connected. It can be confusing when debugging. Change-Id: I46a006f4024b12d27ae0a933b7c40515034d5d64 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16intelblocks/gpio: Optimize GPIO functions by passing group and pin infoMaulik V Vaghela
There were 3 different functions in gpio.c file which used to get gpio group and pin information separately through function calls. Since these are static function, we can modify argument to pass group and pin information from parent/calling function. This will reduce redundant work of getting information 3 times separately. BUG=None BRANCH=None TEST=code compiles and correct information is passed to functions. Check by using pin information on Brya. Change-Id: Ie92be8c22838ebc5e831be58545e2023eecfff24 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Disable PCIe WLAN pinsReka Norman
Nivviks uses CNVi WLAN, so disable the PCIe-related GPIOs. BUG=b:218929856 TEST=Boot to OS on nivviks and check that WLAN still works. Change-Id: I68f12490b0f09658e1307828b0e4488504f50e61 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Add support for NVMe and UFSReka Norman
Enable either eMMC, NVMe or UFS based on fw_config. NVMe and UFS are only supported on nirwen, an additional nissa variant based on nivviks and sharing the nivviks coreboot target. BUG=b:218929856 TEST=Boot to OS on nivviks to check that eMMC still works. NVMe and UFS will be tested once nirwen boards are available. Change-Id: Ibdb122ef35920c962d7bd9f3f238a5d548112282 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Update GPIOs to support nirwenReka Norman
Nirwen is an additional nissa reference board which is almost identical to nivviks, so is reusing the nivviks coreboot variant. However, there are two GPIO changes, so update the GPIO tables to handle these based on board_id. nivviks: GPP_D6 -> WWAN_EN GPP_E13 -> NC nirwen: GPP_D6 -> SSD_CLKREQ_ODL GPP_E13 -> WWAN_EN BUG=b:218929856 TEST=Boot to OS on nivviks Change-Id: I494ed127714069a8f36d16d11ca4e8a1f3d37827 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Disable pen garage based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Set fw_config in CBI and check that pen garage is enabled/disabled as expected. Change-Id: I2c3f5403e0f11443ad3647b8c4ae624f0b88a111 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Disable MIPI WFC based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Change fw_config in CBI and check that WFC is enabled/disabled as expected. Change-Id: Iac4bb358d904579376e0810f8c2644b3bde4f1e6 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/brya: Remove Rcomp resistors override for NissaUsha P
This patch sets the RComp resistor values to default values needed. BUG=b:231202733 TEST=Build and boot nivviks and nereid. Verify the Rcomp values are set to default values from debug FSP log. [SPEW ] Updating Rcomp Targets: [SPEW ] RcompTarget[RdOdt]: 48 [SPEW ] RcompTarget[WrDS]: 30 [SPEW ] RcompTarget[WrDSCmd]: 20 [SPEW ] RcompTarget[WrDSCtl]: 20 [SPEW ] RcompTarget[WrDSClk]: 20 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I2c7a54c49e282446ece77ca406951782282a009a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16mb/google/brya/var/crota: Enable DRIVERS_GENESYSLOGIC_GL9750Terry Chen
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Crota. BUG=b:231686917 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ie10167e48256a61801b2623ae4500db5e67e73cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16arch/x86/null_breakpoint: Remove handler before jumping to payloadArthur Heymans
If a payload did any NULL dereferencing it would be broken and jump back to coreboot code. This fixes the SeaBIOS, FILO and possibly other payloads too. Fixes: 3f01cd14533f ("arch/x86: Add support for catching null dereferences through debug regs") TESTED on qemu/i440fx. Change-Id: I80f69b71f4d0fab3126e4b9f8c8dc7737b372174 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64345 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Stefan Ott <coreboot@desire.ch> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16intelblocks: Add function to program GPE_EN before GPIO lockingMaulik V Vaghela
Since coreboot locks GPIO registers after GPIO configuration, OS is not able to program GPE_EN register to program wake events. This causes the issue of event not getting logged into event log (since GPE_EN bit is not set). GPE_EN register programming is required for the GPIO pins which are capable of generating SCI for the system wake. Elog mechanism relies on GPE_EN and GPE_STS bit to log correct wake signal. This patch add supports to program GPE_EN register before coreboot locks the GPIO registers. Note that coreboot will only program GPE_EN bits for GPIO capable of generating SCI. This will help resolve issue where we don't see wake event GPIO in event log. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Compile code for Brya and see GPE_EN bits set from the kernel console Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16soc/inte/*/gpio; Add GPE_EN and GPE_STS register definitionMaulik V Vaghela
coreboot needs to set GPE_EN bit for the GPIOs which are wake capable from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not be able to write GPE_EN register post GPIO has been locked. This patch adds support in SoC code to provide correct offset for GPE_EN and GPE_STS registers to the common code. Plan is to use this offsets to set GPE_EN bits before GPIO locking in coreboot which will be part of subsequent CL. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Check if code compiles for Brya and correct offset values are printed. Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/crota: Change ELAN touchscreen i2c address and HIDTerry Chen
Change ELAN touchscreen i2c address to 0x16 and change HID to ELAN900C BUG=b:231684121 TEST=local build and tested with ELAN touch screen Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ide005a0681e236c3102090c1c36ab81926849000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16mb/google/nissa/var/nivviks: Disable SD card based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD card is enabled/disabled as expected. Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16drivers/i2c/tpm: Work around missing firmware_version in Ti50 < 0.0.15Reka Norman
Ti50 firmware versions below 0.0.15 don't support the firmware_version register and trying to access it causes I2C errors. Some nissa boards are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading the firmware version and select it for nissa. The firmware version is only read to print it to the console, so it's fine to skip this. This workaround will be removed once all ODM stocks are updated to 0.0.15 or higher. A similar workaround Kconfig was added in CB:63011 then removed in CB:63158 which added support for separate handling of Cr50 and Ti50. But we actually still need this workaround until all Ti50 stocks are upgraded to 0.0.15 or higher. BUG=b:224650720 TEST=Boot to OS on nereid with Ti50 0.0.14 Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-16mb/google/nissa/var/nivviks: Use interrupt with lock for pen detect GPIOEric Lai
With GPIO_DRIVER_LOCK kernel driver can't change to IRQ. Thus, we need to set it as INT in coreboot to make the IRQ work. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16soc/intel/common: Use mp_run_on_all_cpus_synchronously for APs MTRR initKane Chen
By using mp_run_on_all_cpus_synchronously to run APs MTRR init, it gurantees the BSP will run post_cpus_add_romcache until all APs finishes _x86_setup_mtrrs task. BUG=b:225766934 TEST=Test on redrix and found the MTRR race condition on AP/BSP is gone. Change-Id: I1fd889f880a0c605e6c739423a434d2adbc12d26 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16cpu/x86/mp_init.c: Add mp_run_on_all_cpus_synchronouslyKane Chen
MTRR is a core level register which means 2 threads in one core share same MTRR. There is a race condition could happen that AP overrides BSP MTRR unintentionally. In order to prevent such race condition between BSP and APs, this patch provides a function to let BSP assign tasks to all APs and wait them to complete the assigned tasks. BUG=b:225766934 Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63566 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/intel/common/block/smbus: Add smbus block read write functionsShelly Chang
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Change-Id: Ib795f25abe5bbd95555b68af39c637d7c93aa819 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64251 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/amd/picasso/acpi: Change GPIO controller interrupt to sharedRaul E Rangel
This change matches what we already do for cezanne. It will allow the GPIO controller to work correctly in windows. BUG=b:175146875 TEST=Boot windows and verify GPIO controller binds correctly and touch screen works. Also boot linux and verify touchpad still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I998e286de18d3e3f8b2fe610d17aef94a6cf5477 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-05-16mb/amd/chausie/devicetree: add USB PHY configurationFelix Held
Specify the USB PHY settings in the devicetree instead of relying on the FSP defaults. The USB PHY configuration for Chausie are taken from the internal UEFI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cc38e6e26d53802773fe3c405415de15cca98a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16mb/lenovo/t60: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad T60 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-16lib/spd: Demote log about using default DDR4 params to NOTICEEric Lai
Demote log level from error to notice. People should aware the SPD decode might be wrong if it's not the support type. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I55f0968b78baaa2fc9a6bbebf6712fb8bfd349f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16sb/amd/agesa/hudson/hudson.c: Use BIT() macrosElyes Haouas
Also, code reformatting to reduce coding style difference. Change-Id: I488050a6ab852520734b16032af9a683a3ad1a46 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16sb/amd/*/*/acpi: Reduce stylistic differencesElyes Haouas
Change-Id: I1375b1d18113000b31266030fd7115e23d7cce5f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16payloads/coreinfo/coreboot_module.c: Remove 'break' after 'return'Elyes Haouas
Change-Id: Icb60115349ef7c4c35635021784138d45c5a8872 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61954 Reviewed-by: Martin L Roth <gaumless@tutanota.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16northbridge/intel/i945: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Iea9630ce7e5bfcc9d1c8699a81bd1c61a0705de8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h: Correct SPD_PERSONALITY_BYTEElyes Haouas
Regarding Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules DDR3 - Document Release 6 (JEDEC Standard No. 21-C Page 4.1.2.11 – 69) memory buffer personality bytes is located at bytes 102 ~ 116. Change-Id: I7d225fb5e80b537b4c0ce1c23b7a4524e9109a7b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16payloads/nvramcui/nvramcui.c: Reformat codeElyes Haouas
Change-Id: If5b4ae7d9f9046e56ca098c0469b503130bc8707 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16cpu/amd: Remove unused <cpu/x86/pae.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/) Change-Id: I4cab4b66c3d123dbb8a948a5596aa4975b31139b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 05:24:37 +0000