diff options
| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-04-21 15:14:23 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-18 20:39:58 +0000 |
| commit | 2afcbc1b214e69b83f7c66efdcfd74cf64b63eb7 (patch) | |
| tree | 21948979805e346660993f2ee72c755bd47323e4 | |
| parent | ecff5215177eee0b01b608f5db6532d3b90222b6 (diff) | |
soc/intel/elkhartlake: Skip FSP Notify APIs
Follow this commit 95986169f (soc/intel/alderlake: Skip FSP Notify APIs)
to skip FSP Notify APIs.
Elkhart Lake SoC deselects Kconfigs as below:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.
When deselecting these Kconfigs, cse_final_ready_to_boot() and
cse_final_end_of_firmware() in the common cse driver will be used
instead as required operations to perform prior to booting to OS.
Check out this CL for further info:
commit 90e318bba (soc/intel/common/cse: Add `finalize` operation for
CSE)
Additionally, create a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/intel/elkhartlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/finalize.c | 11 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 467662946d..74e003d5af 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -65,8 +65,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_202005_BINDING select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM - select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config MAX_CPUS int diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index 493a3ad7c8..d6ab737de4 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -6,6 +6,7 @@ #include <cpu/x86/smm.h> #include <device/mmio.h> #include <device/pci.h> +#include <intelblocks/cse.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> @@ -30,12 +31,22 @@ static void pch_finalize(void) pmc_clear_pmcon_sts(); } +static void heci_finalize(void) +{ + heci_set_to_d0i3(); + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + heci1_disable(); +} + static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); apm_control(APM_CNT_FINALIZE); + if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && + CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + heci_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); |