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2021-09-05soc/intel/common/cse: Add argument for CSE fixed client addrRizwan Qureshi
There are multiple HECI clients in the CSE. heci_send_receive() is sending HECI messages to only the MKHI client. Add an argument to heci_send_receive() function to provide flexibility to the caller to select the client for which the message is intended. With the above change heci_send() and heci_receive() functions are no longer required to be exposed. In the follow-up patches there will be messages sent to one other client. BUG=None BRANCH=None TEST=Build and boot brya. HECI message send and receive to MKHI client is working. Also, MEI BUS message to disable bus is working. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05soc/intel/alderlake: Add tpch device information under dptfSumeet Pawnikar
Add tpch device information for thermal functionality under dptf for alderlake soc based platform. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05drivers/intel/dptf: Add new thermal control mechanism for pch deviceSumeet Pawnikar
Add new thermal control mechanism for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05mb/google/dedede/var/gooey: Configure I2C times for I2C devicesstanley.wu
Configure I2C high / low time in device tree to ensure I2C CLK runs under I2C_SPEED_FAST (400 kHz). Measured I2C frequency just as below after tuning: Touchpad: 386.7kHz Touchscreen: 387.4kHz Audio: 385.7kHz P-sensor: 378.1kHz BaUG=b:197247706 BRANCH=dedede TEST=Build and check I2C clock is under 400kHz Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Ic5d5660181f36f161ae04cbf5003f6d7ad4bc16f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-05mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem moduleStanley Wu
Add MT53E512M32D1NP-046 WT:B supported memory part in the mem_parts_used.txt and generate the SPD ID for the part. Manufacturer is Micron, and the memory part is 1anm Tech, difference to 1xnm Tech on MT53E512M32D2NP-046. BUG=b:194223174 BRANCH=dedede TEST=Build the gooey board. Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57310 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-05soc/intel/common: Add PMC IPC commands for FIVRSumeet Pawnikar
Add PMC IPC commands information for FIVR control functionality. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05soc/intel/jasperlake: Utilize vbt data size Kconfig optionSeunghwan Kim
Currently maximum VBT data size for Jasper Lake is 8KB, but Bugzzy would use VBT data over 8KB. This change makes use of Kconfig option to increase the maximum VBT data size to 9KB for Jasper Lake. BUG=b:194029827 BRANCH=dedede TEST=build and boot bugzzy and verify fw screen is loaded Change-Id: I0abe1ba5609b48a8a8b15f88bec28342ce26c78f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57201 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-05mb/google/dedede/var/drawcia: change LTE reset pin to GPP_H17Wisley Chen
Drawper change LTE reset pin from GPP_H0 to GPP_H17 from DVT phase. BUG=b:198117092 TEST=emerge-dedede coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ib65580babf7d21535df2bd8d33bb19261bebfe15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
2021-09-05mb/intel/adlrvp: Clean up the print messageBora Guvendik
TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I6346b087543217c78f87751051a4f38b23c566d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-09-05mb/google/guybrush: Set eSPI alert as dedicated open drainRob Barnes
Guybrush based boards must usa a dedicated eSPI alert#. Must be open drain to prevent power leaks. Keep guybrush reference board in-band since alert# may not be connected. BUG=b:198409370 TEST=Build guybrush and nipperkin, boot guybrush BRANCH=None Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-05soc/intel/elkhartlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-05soc/intel/cannonlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: I6ae22f9df4834508dfa304050fad44d45df45334 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-05soc/intel/jasperlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: I10f859f30b260d012f0bc8755f32413d8b2cf267 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-05smbios.c: Rename two local functionsAngel Pons
Rename two functions that have `walk` in their name but do not perform any walk. The new names are derived from the comments just above these functions' definitions. Also, remove these now-redundant comments. Change-Id: I380a5b60b3f4e820e8f6d6f960826de97c0446be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57361 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-05drivers/intel/fsp/Makefile: error out when FSP files aren't specifiedFelix Held
Error out when the FSP binaries that are supposed to be added aren't specified. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ie5f2d75d066f0b4e491e9c8420b7a0cbd4ba9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIESFelix Held
Like USE_AMD_BLOBS and USE_QC_BLOBS in the case of the AMD and Qualcomm repos, FSP_USE_REPO controls if the Intel FSP repo will get checked out and will be available during the Jenkins runs. ADD_FSP_BINARIES will get selected in drivers/intel/fsp2_0/Kconfig when FSP_USE_REPO is selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I72faa6f9e5f2b06ab7cd43595ae0b49bf4d39630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05mb/intel/leafhill,minnow3: remove FSP_M_CBFS and FSP_S_CBFS overrideFelix Held
The overrides set the options to the same value as drivers/intel/fsp2_0/ Kconfig does, so drop the overrides. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53922786382a2e7d29b3df560a1998f41e1d2ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05mb/intel/leafhill,minnow3: remove FSP_M_FILE and FSP_S_FILE overrideFelix Held
Normally, selecting FSP_USE_REPO will select FSP_FULL_FD which then will configure the proper paths for FSP_M_FILE and FSP_S_FILE. The override in these two boards caused FSP_M_FILE and FSP_S_FILE being empty despite ADD_FSP_BINARIES being selected by FSP_USE_REPO which is an invalid case that needs to be avoided, so remove the board-level override of those two options. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I20c8cebea8327d59f0f33d05b824a74bf2121f4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05mb/intel/leafhill,minnow3: remove ADD_FSP_BINARIES config overrideFelix Held
The ADD_FSP_BINARIES override in the mainboard's Kconfig caused this option to not be selected when FSP_USE_REPO is selected. Remove the override to fix this problem. These two boards are the only ones in tree that had an override for this option, so now the ADD_FSP_BINARIES option is only defined in drivers/intel/fsp2_0/Kconfig. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23439f3134eef9460625addbff7efd64c5f65ae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05sb/amd/pi/hudson: drop HUDSON_UART option and corresponding codeFelix Held
This option is neither selected nor usable for the only remaining SoC that uses this code, so drop the remaining parts. configure_hudson_uart isn't called anywhere and isn't even compiled, since it's guarded by an #if CONFIG(HUDSON_UART) block and the HUDSON_UART Kconfig option isn't selected anywhere. Both the offsets used in the iomux_write8 calls and the UART controller itself aren't listed in the BKDG #52740 Rev 3.05 for the AMD Family 16h Models 30h-3Fh APUs which is the only SoC that uses this code, so the code didn't even apply for this chip. TEST=Timeless build for pcengines/apu2 results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3f462d1f83a0f1ba851329ebebb1f3263267fdc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-04configs/config.google_meep_cros: don't select ADD_FSP_BINARIESFelix Held
This config selected ADD_FSP_BINARIES even though HAVE_INTEL_FSP_REPO is only defined for Apollolake and not Geminilake that resides in the same SoC directory and uses the same Kconfig file. This results in the paths to the FSP binaries not being defined, in which case the ADD_FSP_BINARIES option shouldn't be selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95123c4930b44a3b76c87768e130eb7359bbf625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-04soc/amd/picasso: select ADD_FSP_BINARIES if USE_AMD_BLOBS is selectedFelix Held
Since the FSP binaries for Picasso are present in the amd_blobs repo, select the ADD_FSP_BINARIES option if the Kconfig option to check out that repo is set. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-04cpu/x86: Use MP_RUN_ON_ALL_CPUS macro instead of hardcodingSubrata Banik
This patch ensures mp_run_on_all_aps() is passing 'MP_RUN_ON_ALL_CPUS' macro rather hardcoding `0` while running `func` on all APs. Change-Id: Icd34371c0d4349e1eefe945958eda957c4794707 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-04sb/amd/pi/hudson/soc/gpio: add SOC_GPIO_TOTAL_PINS definitionFelix Held
EGPIO132 is the last documented GPIO on the GPIO controller in the NDA version of the BKDG for AMD Family 16h Models 30h-3Fh Processors (#52740 Rev 3.06) which is the only SoC using this code, so define SOC_GPIO_TOTAL_PINS as 133, since the internal GPIO numbers are 0-indexed. This definition will be needed the subsequent patch that'll add the remote GPIO support to the common AMD GPIO code to make sure that the compiler can optimize out the code path needed to support the remote GPIO access which isn't available on this platform anyway. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I877d462c5e753c9bbb3461dbb10cde2adc2cb12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-04mb/google/volteer: Move EC_HOST_EVENT_USB_MUX wake event to S0ix onlyTim Wawrzynczak
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown transtion (S0->S3->S5), this will cause the device to boot again after it has finished sequencing down to S5. Since S3 is not POR for ChromeOS devices anymore, change this event to wake from S3 and S0ix to just S0ix. BUG=b:197039097 TEST=abuild Change-Id: I91e5e0ab8301377817875b6fa9e3c0e1f96c1465 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-03util/liveiso: Add NixOS configs for bootable live systemsFelix Singer
Add NixOS configurations for bootable live systems containing a set of tools which might be useful for firmware development in general and for working on coreboot. There are two configurations provided. One for console-only and a graphical one, which is mostly the same as the console image but it comes with Gnome Shell as window manager and some graphical tools in addition. An image can be built using `build-console.sh`, respectively `build-graphical.sh`. The resulting iso image can be found in `result/iso/`. The console image results in ~700MB, while the graphical one results in ~2GB. Change-Id: Iaf49d198e99781434bd89d2a8a125a4988b77e1c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-03arch/x86: Update debug message to callout the reason for failureSubrata Banik
This patch updates debug message to specifically the case when SMBIOS table 7 write would abort due to either `unknown` CPU or CPU `doesn't have support for deterministic cache cpuid leaf`. Change-Id: I288593b3f78ab858bf66c689e7cfb6ba2ff746d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-03arch/x86: Check unsupported CPU type while writing to SMBIOS table 7Subrata Banik
Don't attempt to fill the SMBIOS table if the CPU doesn't support deterministic cache CPUID. TEST=Able to fix the hang issue seen on ASRock E350M1 with commit hash e2b5fee. Change-Id: Id65dc963e235f7080370a32cf69bcc4bee94d28f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57306 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03arch/x86: Skip returning default leaf value as `0`Subrata Banik
`cpu_get_cache_info_leaf()` function is responsible to report leaf value for CPU that have support for deterministic cache cpuid. As per available datasheets from AMD and Intel the supported CPUID leafs are 0x8000_001d for AMD and 0x04 for Intel. Hence, this CL skips returning default leaf value as `0`. TEST=Verified fixes: e2b5fee3b006 (arch/x86: smbios write 7 table using deterministic cache functions) hang issue on ASRock E350M1. Change-Id: Iee33b39298e7821ac5280d998172b58a70c8715b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57305 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03sc7280: Refactor QSPI driverRoja Rani Yarubandi
Refactor Qcom QSPI driver to separate common and SoC specific driver code. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: Ibe1dc3fe8bd71957ff8604ef4c9d97963100ccfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03mb/google/brya/variants: fix override values for power limitsSumeet Pawnikar
There are two different types of 682 SKU available with TDP of 28W and 45W. This patch fix override values for power limits for these 682 SKU. This patch also sets power limit values dynamically based on machine ID and CPU TDP of SKU. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I796e56321ae9c8312530a4b8986cd73a2245f5fa Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57290 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03soc/qualcomm/common/qspi: Add support for common QSPI driverRavi Kumar Bokka
copy existing QSPI driver from /soc/qualcomm/sc7180 to common folder. This common QSPI driver works in master mode and provides read/write operation for the slave devices like flash. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03soc/qualcomm/sc7280: DDR One-Time-Training SupportRavi Kumar Bokka
Introduce DDR One-Time-Training Support Device reboots without training from second iteration and also DDR training data is 32kb size, hence update required in memlayout and to sync with upstream changes the Fmap size even got bumped up. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03mainboard/google/herobrine: Configure SDCC clockShaik Sajida Bhanu
Configure 384MHz for eMMC clock and 50MHz for SD card clock. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I8acbce58614add0228adc39289762da10937cbe2 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03qualcomm/sc7280: Move to use common clock driver for sc7280Taniya Das
It supports the clock consumers for QUP, SDCC, PCIE, Display to be able to configure & enable the desired clocks. The clock driver also supports reset of subsystems like AOP and SHRM. Also add support for Zonda PLL enable for CPU in common clock driver. Refactor the SC7280 clock driver to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03mb/intel/adlrvp_m: Fix TPM IRQ conflict with I2C4Selma Bensaid
Add TPM IRQ config to gpio_m.c, so the TPM IRQ is not allocated to I2C4. BUG=NA BRANCH=None TEST= boot to os and check cat /proc/interrupts, cr50 SPI interrupt is assigned and does not conflict with I2C. CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 0: 36 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 2-edge timer 1: 0 0 0 0 0 0 0 0 9 0 0 0 IO-APIC 1-edge i8042 8: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC1055:00 16: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 16-fasteoi intel-ipu6 22: 0 13 0 0 0 0 0 0 0 0 0 0 IO-APIC 22-fasteoi idma64.4, i801_smbus, ttyS0 37: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 38-fasteoi idma64.1, i2c_designware.1 41: 0 0 0 0 2274 0 0 0 0 0 0 0 IO-APIC 41-edge cr50_spi 42: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 42-fasteoi idma64.2, i2c_designware.2 43: 4 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 43-fasteoi idma64.3, i2c_designware.3 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: Id0f3885dec5a6f635254c233709090321491c739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57102 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03soc/intel/alderlake: set power limits dynamically for thermalSumeet Pawnikar
Set power limit values dynamically based on CPU TDP and PCI ID of SKU. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03soc/intel/common: get tdp of CPU for different SKUsSumeet Pawnikar
Get tdp value of CPU for different SKUs based on PKG POWER MSR. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-03mb/pcengines/apu2: add and use IOMUX definesFelix Held
Add GPIO IOMUX defines for the pins that are used in the mainboard code which enables using the PAD_GPI and PAD_GPO macros. TEST=Timeless build for APU2/3/4/5 results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-09-03soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chipsFelix Held
southbridge/amd/pi/hudson uses the common GPIO bank access code from soc/amd, but doesn't provide all functionality that would be needed to use the full functionality. Add a Kconfig option that switches off some functionality in the common SoC GPIO access code, so that more of the functionality proviced by the common SoC GPIO code can be used in the AMD binaryPI chipset and board code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03mb/pcengines/apu2/gpio_ftns.h: add comment about GPIO numbersFelix Held
The mapping of the package GPIO numbers to the GPIO numbers on the GPIO controller isn't a 1:1 one, so add a comment about that to avoid confusion. Also change the comment style to match the style guide. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie30bf5483ea2e2516d7e3fdd21ea9338362e526e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-09-03mb/pcengines/apu2/romstage: use proper GPIO configuration APIFelix Held
Also remove the unused amdblocks/acpimmio.h include in gpio_ftns.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: If121941c8a6ba88913653192740997aeef426548 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56784 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03mb/google/dedede/var/bugzzy: Configure DDI port A as MIPI DSISeunghwan Kim
Override DdiPortAConfig as MIPI DSI BUG=b:192521391 BRANCH=None TEST=Built test coreboot image and boot on bugzzy board Change-Id: If308f9d69fea56176527e7b67f36b29c43adb525 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-03drivers/intel/fsp2_0/Makefile: add condition for FSP-T CBFS fileFelix Held
Make adding the FSP-T file to CBFS depend on both ADD_FSP_BINARIES and FSP_CAR Kconfig options being set. The FSP_T_FILE Kconfig option depends on both, so also check if both are selected in the Makefile where it tries to add the FSP-T to the CBFS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Id347336f2751c6d871f31d89c30a1222037c2d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-03vc/mediatek/mt8195: Remove unused codeRyan Chuang
Remove unused drivers and some fast calibration implementations to align with the latest MTK memory reference code. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I3b235cbceb231898f00fce7905f596eab54ca595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03soc/qualcomm/common: clock: Add support for common clock driverTaniya Das
The clock driver supports configuring the general purpose PLLs, configuring the root clock generator (RCG), enable clock branch, enable gdsc and also the block resets. The common clock driver exposes PLL configuration functions and also different Agera PLL enable functions for the CPU PLLs. While at it, the common driver also supports reset of subsystems like AOP and SHRM. SC7180 clock driver is also refactored to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03qualcomm/sc7180: Clean up drivers with common clockTaniya Das
As we move to use the common clock driver, the sc7180 clock driver, watchdog and display drivers requires few cleanups, thus update the impacted drivers. Earlier the display client is expected to provide 2n divider value, as the divider value in register is in form "2n-1". mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0; The older convention in the upcoming patches would be replaced with the common macro of QCOM_CLOCK_DIV, thus need the divider needs to be updated. mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0; To accommodate impacting the functionality, the half_divider is taken care in the clock driver. BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03mb/intel/adlrvp: Move common Kconfig from mb Kconfig.name to KconfigSubrata Banik
CONFIG_DRIVERS_INTEL_MIPI_CAMERA and CONFIG_SOC_INTEL_COMMON_BLOCK_IPU are getting selected for all ADLRVPs irrespective of ADL-P and ADL-M (internal and external EC SKUs) hence, select those Kconfigs from mainboard Kconfig rather Kconfig.name. Also, select DRIVERS_INTEL_SOUNDWIRE as per alphabetical order. TEST=No changes are seen while the .config file is getting auto generated. Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-03skylake: Default to `BOARD_TYPE_DESKTOP` for PCH-HAngel Pons
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H. Remove now-redundant mainboard code to set the `UserBd` UPD. Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03mb/prodrive/hermes: Do not overwrite `IedSize` UPDAngel Pons
SoC code already sets this UPD to `CONFIG_IED_REGION_SIZE`, which defaults to 0x400000 for soc/intel/cannonlake. Change-Id: I6587e17a4a3425c561cffe6e3df0d932a2458168 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-03mb/prodrive/hermes: Use `BOARD_TYPE_SERVER` defineAngel Pons
Change-Id: I291dc71bb6e3888b71ebce315f9ad09ccbc4a9a7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-03src/*: Specify type of `DIMM_MAX` onceAngel Pons
Specify the type of the `DIMM_MAX` Kconfig symbol once. Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-03src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-02mb/google/guybrush: Update PCIe WWAN path for WWAN PCIe checkMartin Roth
variant_has_pcie_wwan() was always coming back as disabled because find_dev_nested_path() couldn't find the device until the domain was added to the array. BUG=b:193036827 TEST=Boot guybrush with PCIe & USB WWAN devices. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Id94fa0b0ff5c29fa447e869220d27ccfe61438c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-02Documentation: add Intel BroadwellIru Cai
Change-Id: I0b1c29162a64030b5c100368f2471702e22b8311 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-02mb/google/brya: reduce RW_MRC_CACHE size to 64KNick Vaccaro
The RW_MRC_CACHE only needs to be 64K for Brya. BUG=none TEST="emerge-brya coreboot chromeos-bootimage", flash and boot brya0 to kernel. Change-Id: I74365b795e184b92f483ae2bf862791e235c5362 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56989 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02wifi: Add support for DSM methods for intel wifi cardSugnan Prabhu S
Add support for DSM methods as per the connectivity document 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:191720858 TEST=Check the generated SSDT tables for DSM methods Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for wifi time average SAR configSugnan Prabhu S
Add support for the WTAS ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the WTAS related configuration values and verified that the SSDT has the WTAS ACPI table. Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for per-platform antenna gainSugnan Prabhu S
Add support for the PPAG ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the PPAG related configuration values and verified that the SSDT has the PPAG ACPI table. Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for new revisions of SAR table entriesSugnan Prabhu S
Existing SAR infrastructure supports only revision 0 of the SAR tables. This patch modifies it to extend support for intel wifi 6 and wifi 6e configurations as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf The SAR table and WGDS configuration block sizes were static in the legacy SAR file format. Following is the format of the new binary file. +------------------------------------------------------------+ | Field | Size | Description | +------------------------------------------------------------+ | Marker | 4 bytes | "$SAR" | +------------------------------------------------------------+ | Version | 1 byte | Current version = 1 | +------------------------------------------------------------+ | SAR table | 2 bytes | Offset of SAR table from start of | | offset | | the header | +------------------------------------------------------------+ | WGDS | 2 bytes | Offset of WGDS table from start of | | offset | | the header | +------------------------------------------------------------+ | Data | n bytes | Data for the different tables | +------------------------------------------------------------+ This change supports both the legacy and the new format of SAR file BUG=b:193665559 TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different binaries generated by setting different versions in the config.star Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabledMeera Ravindranath
GPIO PM was disabled for brya to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. All devices currently tested on brya support 4us long pulses. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot brya to OS, ensure no TPM errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56926 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02drivers/mipi: Make orientation a property of the mainboard, not panelJulius Werner
It doesn't make sense to store the orientation field directly in the panel information structure, which is supposed to be reuseable between different boards. The thing that determines orientation is how that panel is built into the board in question, which only the board itself can know. The same portrait panel could be rotated left to be used as landscape in one board and rotated right to be used as landscape in another. This patch moves the orientation field out of the panel structure back into the mainboards to reflect this. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If2b716aa4dae036515730c12961fdd8a9ac34753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02mb/google/brya/variants/brask: Enable PCIE port 7 for EthernetDavid Wu
Enable PCIE port 7 using clk 6 for RTL8125 Ethernet BUG=b:193750191 BRANCH=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16Tim Crawford
TGL-H supports up to 8 cores (16 threads). Change-Id: I2ee1be37f564bf1b6249a6c223be093747c38ab5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02mb/system76/*: cmos.layout: Reserve century byteTim Crawford
Windows will write to the century byte (0x32), causing the option table checksum to be invalid and reset all options to their default values. Move options and checksum to start after the century byte. Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-02mb/google/guybrush/nipperkin: update DRAM tableKevin Chiu
MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR BUG=b:194031783 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I71ceaf0a2738584d316a5b7cc51539821b430128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-09-02mb/google/zork: correct MST probesPeter Marheine
It turns out that putting a device ref in an overridetree at a different point in the tree will generate a duplicate device definition, such that the change introducing this support was ignoring the device presence specified by overridetree.cb and only using the baseboard configuration. I believe testing of that change was not redone after the baseboard was changed to disable the MST, so that conflicting behavior was not noticed. The incorrect behavior generated a disabled device for the MST at the location specified by the baseboard, and one with the probe as a child of the soc. At runtime this did a fw_config probe of the "I2C 00:4a" device, and later probed a different "I2C 00:4a" which was already disabled. As the disabled one came later, it seems to have completely disabled the MST, discarding the results of the variant-specific probe. BUG=b:185862297 TEST=10EC2141 device is now present on a Dali berknip BRANCH=zork Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57298 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02util/cbftool: Fix the bug in parsing Uefipayload with extended headerDun Tan
The patch is to fix "Not a usable UEFI firmware volume" issue when creating CBFS/flash image. This issue is caused by adding FvNameGuid in UefiPayloadEntry.fdf in EDKII. There is an ext header between header of Fv and header of PayloadEntry in Fv with FvNameGuid. The ext header causes the UefiPayloadEntry to be found incorrectly when parsing Fv. Commit in EDKII: 4bac086e8e007c7143e33f87bb96238326d1d6ba Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=3585 Signed-off-by: Dun Tan <dun.tan@intel.com> Change-Id: Id063efb1c8e6c7a96ec2182e87b71c7e8b7b6423 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57296 Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02tests: Add lib/cbfs-verification-test test caseJakub Czapiga
This commit adds test case for lib/cbfs verification mechanisms. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I1d8cbb1c2d0a9db3236de065428b70a9c2a66330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56601 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01cbfs: Make sure all cases of single file header corruption are isolatedJulius Werner
The new CBFS stack was written to try to isolate cases of single file corruption as far as possible and still make other files avaialble (at least as long as verification is disabled and they can still be found at all). For most cases of header corruption, it will just continue trying to parse the next file. However, in cases where parts of the file extend beyond the end of the rdev, we have been relying on the range checking of the rdev API rather than doing it explicitly. This is fine in general, but it causes the problem that these errors cannot be distinguished from I/O errors, and I/O errors always make the whole cbfs_walk() fail. That means we will not return a successful result from cbfs_mcache_build(), and leads to an odd discrepancy in how certain kinds of corrupted CBFSes are treated with and without mcache. This patch adds an explicit range check to make the behavior consistent. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ice2b6960284bd0c19be35b0607e5e32791e7a64c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-09-01tests: Improve test output readabilityJakub Czapiga
When running multiple tests, e.g. by using unit-tests target, it is hard to differentiate, which output comes from which file and/or configuration. This patch makes the output easier to analyze and understand by using new wrapper macro cb_run_group_tests(). This macro uses __TEST_NAME__ value (containing test path and Makefile test name) as a group name when calling cmocka group runner. Example: Test path: tests/lib/ Makefile test name: cbmem_stage_cache-test Test group array name: tests Result: tests/lib/cbmem_stage_cache-test(tests) Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I4fd936d00d77cbe2637b857ba03b4a208428ea0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-01soc/amd/cezanne: Increase the FSP_M_SIZE configurationKarthikeyan Ramasubramanian
On mainboards with Cezanne SOC, serial enabled FSP_M binary size is greater than the size allocated in DRAM. Increase the allocated size for FSP_M binary in DRAM to handle both debug and release FSP_M binaries. Also adjust the verstage load address accordingly. BUG=None TEST=Build and boot to OS in guybrush with both debug and release FSP_M. Perform warm, cold reboot and suspend/resume cycling for 10 iterations. Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01libpayload: Move EXTRA_CFLAGS to enable option overrideJakub Czapiga
Before this patch EXTRA_CFLAGS were placed before many other options. This made overriding impossible even, when necessary. This patch moves EXTRA_CFLAGS to be placed after original CFLAGS, thus making option overriding possible. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If8394b151696eee4bd736d2fb1ad340209e05fbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/57181 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01mb/goog/brya: Add probed fw_configs to SMBIOS OEM stringsWisley Chen
Enable this feature, and it can use the probe statement in devicetree to cache of fw_config field as oem string. BUG=b:191931762 TEST=With CBI FW_CONFIG field set to 0x8, set probe AUDIO MAX98390_ALC5682I_I2S_4SPK in devicetree dmidecode -t 11 OEM Strings AUDIO-MAX98390_ALC5682I_I2S_4SPK Change-Id: I93cd9ef2d1ad963e66c422cff17b083abf731046 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01util/sconfig: Compare probe conditions for override device matchFurquan Shaikh
When the override functionality looks for device match, check that the probe list for both the devices matches exactly if probe list exists for the base device. This ensures that if there are two devices with same identity (e.g. I2C address or USB port #) but using different properties (registers) controlled by different probe statements, then the two devices are not incorrectly matched as the same device. The check for base device having a probe list is performed before comparing the probe lists because a base device might not really have any probe requirements at all. So, when overriding such a device, there is no need to check for the probe list match. BUG=b:187193527 TEST=Verified by adding two I2C devices in the override tree with the same I2C address and chip but different probe statements and confirmed that both the devices are present in generated static.c file. Change-Id: Ib18868b336cf4ffc9aa38aee7c6f333a35d32fce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-01mb/google/volteer: Move hda device enabling to override treeFurquan Shaikh
This change moves the hda device enabling from baseboard device tree to override tree for the variants that did not provide any hda specific nodes. This ensures that the probe statements are correctly selected by the variant depending upon the configurations it supports. Change-Id: Ib7b36468f17fbd65eb3d7d9355fcf78148aeb44a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57123 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01mb/google/volteer: Fix USB4 enabling for volteer familyFurquan Shaikh
volteer baseboard was currently enabling TBT(USB4) devices in baseboard devicetree and also selecting the Kconfigs required for resource allocation above 4G for the USB4 controllers. However, not all volteer devices have USB4 support. This change fixes USB4 enabling for volteer family by making the following udpates: 1. TBT devices are moved from baseboard devicetree to individual override trees for the variants that actually support USB4. 2. When moving TBT devices to override tree, tbt_pcie_rp0 is marked as on instead of hidden for all variants other than volteer reference. This is because volteer reference is the only device that has an asymmetric support for USB4 (i.e. does not support USB4 on C0 port). 3. Kconfig selection for PCIEXP_HOTPLUG is moved to Kconfig.name for these variants. Change-Id: If380dcb1ea1633b3a1d6932e769cb6ed0a2761c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57112 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01soc/intel/alderlake: Fix processor hang while plug unplug of TBT deviceSugnan Prabhu S
Processor hang is observed while hot plug unplug of TBT device. BIOS should execute TBT PCIe RP RTD3 flow based on the value of TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if BIT30 in TBT FW version is not set. BUG=b:194880254 Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01mb/google/brya/var/redrix: adjust uid for Maxim ampWisley Chen
DEV0 - 0x3a i2c-MX98390:00: Right Speaker DEV1 - 0x3b i2c-MX98390:01: Left Speaker DEV2 - 0x38 i2c-MX98390:02: Right Tweeter DEV2 - 0x39 i2c-MX98390:03: Left Tweeter This is to consist with other 2 speakers configs, and m/c driver design. uid0/1 = regular speakers. uid2/3 = tweeter BUG=191931762 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0a3183b1e1ecbb109258d6e076551158e0b40ce1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01Doc/mb/ocp: Add hyperlink to src/mainboard/ocp/deltalake/vpd.hJohnny Lin
It would be easier for people to find the defined variables. Change-Id: I6d181f6602aa5d55019ea2110b2d8e1fa7e0159c Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-09-01drivers/intel/fsp1_1/romstage.c: Remove MCU updateArthur Heymans
On Braswell this is done in the bootblock before C code is executed. Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-09-01soc/amd/common: Change default spi speeds to 33MHzMartin Roth
In CB:56884 we discussed changing the default fast_read speed from 66MHz, which some platforms may not be capable of running, to 33MHz, which should be generally suitable for all platforms. This same change has been applied to the default for all SPI speeds. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57148 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31cbfstool: add buffer_end() to common.hRicardo Quesada
Add buffer_end() function to common.h. This function returns a pointer to the end of the buffer (exclusive). This is needed by elogtool util. (See the next CL in the chain). BUG=b:172210863 Change-Id: I380eecbc89c13f5fe5ab4c31d7a4fef97690a791 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-31arch/x86: Implement cpu_info in C codeArthur Heymans
Change-Id: Ic7396b8429e29739e18a189dacea3a76e571cd58 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57049 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31mb/google/dedede/var/cret: Modify Wifi SAR conditionIan Feng
Using tablet mode of fw config to decide to load custom wifi sar or not. BUG=b:194163604 TEST=build and test on cret and cret360 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ie94c2a07ad43fe1cb426e543dd97ed0434c42f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-31soc/amd/*/include/soc/gpio: remove GPIO_2_EVENTFelix Held
commit de7262f82cdc1a7c868dbc9ca41e186e885eb2ba (soc/amd: remove special GPIO_2 override soc_gpio_hook) removed the workaround that needed those definitions, so remove the now unused GPIO_2_EVENT definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3f3e3061eade0e0cd25e2263451ccf6cefdc4ea4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56812 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31smbios.c: Move function definition near call-siteAngel Pons
The `smbios_get_device_type_from_dev()` function is only called once from the `smbios_walk_device_tree_type41()` function. Put the former function's definition above the latter function's, instead of having them a thousand lines apart. Change-Id: Idc6175324ca8a14841eaf7d6904712efb75f2d26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57205 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31mb/google/brya/var/gimble: Include SPD for K4UBE3D4AA-MGCRMark Hsieh
Add SPD support to gimble for LPDDR4 memory part K4UBE3D4AA-MGCR. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ida21fd50129412af59a341dea45232fd0f9931ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/57253 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31mb/razer/blade_stealth_kbl: Disable UART #0 in devicetreeAngel Pons
FSP-S disables UART #0 as per the `SerialIoDevMode` settings. Change-Id: Ic1f9f7ce6fd4f453200d563bd8556946eef1b287 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Mimoja <coreboot@mimoja.de>
2021-08-31mb/google/caroline: Enable I2C #2 in devicetreeAngel Pons
Commit 98ec53bdf15ff79369307862e71142d4606f9e5a (mb/google/caroline: Re-enable I2C2 / fix digitizer) enabled I2C #2 in the `SerialIoDevMode` array, but left the device disabled in the devicetree. Enable it. Change-Id: I67eec1c753bfd2a78ed0c1e0a78057cd4a3d4153 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-08-31mb/google/poppy: Do not let FSP-S init UART 0Angel Pons
FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy boards only enable UART 0 because it's function 0 of PCI device 30, and the PCI specification requires that function 0 of multifunction devices be implemented if other functions are implemented as well. Nautilus got remedied in commit 8a1f095e50e068e42d378f47c79467e7b6295b7b (mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the SerialIO device. This way, it remains enabled and the GPIO settings will not be overwritten by FSP. However, not all variants do this, but use some UART 0 pads as GPIOs. To prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the variants. Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55236 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31amdfwtool: Add flag for multi FW level to the struct amd_cb_configZheng Bao
This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31amdfwtool: Copy string in a safer wayZheng Bao
The issue is reported by Coverity. Using strcpy or strcat copying string without checking length may cause overflow. BUG=b:188769921 Reported-by: Coverity (CID:1438964) Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd/cezanne/fch: implement and use fch_clk_output_48MhzFelix Held
Make sure that the 48MHz clock output that is typically used as a clock source for an I2S audio codec or a Super I/O chip. TEST=On Guybrush before and after this patch the final state of MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/(amd,google): Remove spi configuration from devicetreeMartin Roth
Now that the SPI configuration has been moved into Kconfig, it is no longer needed in devicetree. BUG=b:194919326 TEST=Build & boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifdcd3f33173194c4a25794137756b143751edd70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd: Show SPI settings in bootblockMartin Roth
BUG=b:194919326 TEST=See SPI settings in bootblock Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd/common: Show current SPI speeds and modesMartin Roth
This patch adds code to print the current SPI speeds for each of the 4 different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays the SPI mode and whether or not SPI100 mode is enabled. BUG=b:194919326 TEST: Display the speed, change speeds, show that new speeds are the expected values. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd/cezanne/early_fch: Perform early SPI initializationKarthikeyan Ramasubramanian
Add the fch_spi_early_init call in fch_pre_init to perform early SPI initialization which enables SPI ROM and setting the speed & read modes. BUG=b:194919326 TEST=Build and boot to OS in Guybrush. Change-Id: Ibfbe6e16bd6b0dd46c13cecf2a35f0c0b4576b88 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56684 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd/common: Update SPI based on Kconfig & EFS instead of devtreeMartin Roth
Get the settings for fast-read and mode from EFS, and reprogram those. Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings. BUG=b:195943311 TEST=Boot and see that SPI was set to the correct speed & mode Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-30soc/amd/common: move GPIO register state save struct to gpio_banks.hFelix Held
The common_i2c_save struct isn't specific to the I2C code and since it contains the state of the GPIO control & status register and the state of the GPIO MUX register, move it to include/amdblocks/gpio_banks.h and rename it to soc_amd_gpio_register_save. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7cd47e5a32427d856948e319de8dfad8c928e96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>