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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-08-26 09:07:44 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-09-05 19:20:11 +0000
commit9ed175167664b63beb19cb656b53cbf6033f6a75 (patch)
treebab4834d9ea5804966f725a85f2e3fcc8d76b2ec
parent12b809bf00f2eaf23ef45c7dfb16233ce0ef517f (diff)
soc/intel/jasperlake: Lock PAM registers in finalize
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: I10f859f30b260d012f0bc8755f32413d8b2cf267 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/intel/jasperlake/finalize.c9
-rw-r--r--src/soc/intel/jasperlake/fsp_params.c1
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c
index 07bfee366b..a60e71916e 100644
--- a/src/soc/intel/jasperlake/finalize.c
+++ b/src/soc/intel/jasperlake/finalize.c
@@ -9,8 +9,10 @@
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/systemagent.h>
#include <intelblocks/tco.h>
#include <intelblocks/thermal.h>
+#include <intelpch/lockdown.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
@@ -80,12 +82,19 @@ static void pch_finalize(void)
pmc_clear_pmcon_sts();
}
+static void sa_finalize(void)
+{
+ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
+ sa_lock_pam();
+}
+
static void soc_finalize(void *unused)
{
printk(BIOS_DEBUG, "Finalizing chipset.\n");
pch_finalize();
apm_control(APM_CNT_FINALIZE);
+ sa_finalize();
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index bb41b28f15..11b146b577 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -75,6 +75,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchLockDownBiosInterface = lockdown_by_fsp;
params->PchUnlockGpioPads = !lockdown_by_fsp;
params->RtcMemoryLock = lockdown_by_fsp;
+ params->SkipPamLock = !lockdown_by_fsp;
/* coreboot will send EOP before loading payload */
params->EndOfPostMessage = EOP_DISABLE;