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2023-10-27soc/amd/genoa: select PSP gen 2 supportFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iffe21fb0c0bff0fc21ce1ac3af71d39bb62fd384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78660 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27mb/google/rex: Update FMD to support CBFS verificationAnil Kumar
This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. These blobs were kept separate originally to avoid hash loading and verification every time and hence save boot time. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed. BUG=b:284382452 TEST=Build CB image for google/rex board and test CSE FW update/downgrade with CONFIG_VBOOT_CBFS_INTEGRATION config enabled. Also confirm there is no increase in boot time with this change. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I56865a9e5c8b5f9e908e00e1a7e7e187d5d6a2f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-10-27soc/intel/cse: remove cbfs_unverified_area_map() API in cse_liteRizwan Qureshi
With CBFS verification feature (CONFIG_VBOOT_CBFS_INTEGRATION) being enabled, we can now remove cbfs_unverified_area_map() APIs which are potential cause of security issues as they skip verification. These APIs were used earlier to skip verification and hence save boot time. With CBFS verification enabled, the files are verified only when being loaded so we can now use cbfs_cbmem_alloc()/cbfs_map function to load them. BUG=b:284382452 Change-Id: Ie0266e50463926b8d377825142afda7f44754eb7 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78214 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2023-10-26mb/google/brox: Add Arbitrage generated gpio.c fileShelley Chen
Checking in gpio.c generated by arbitrage. Used this command line to generate: arb export-coreboot-gpio --refdes=U1 brox:proto1_20231017 BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I1098bd4cfde393ed9e78cd90158c3534fdf0dc09 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78657 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26mb/google/brox: use Alderlake-P SoC instead of Alderlake-SShelley Chen
Skolas is actually using the SOC_INTEL_ALDERLAKE_PCH_P config, so fixing Brox to reflect this as it's using the same SoC. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I632ec055d523956983d2053cd8e7000b1eaabf92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78656 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26mb/prodrive/hermes: Rework UART devicetree entryMatt DeVillier
Rework the UART devicetree entry so that it doesn't conflict with the to-be-added chipset devicetree for CNL. This should be functionally equivalent to the previous entry, but needs testing to verify. Change-Id: Iae60cb8e0746e7dc2928da3687762b81928fb5f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78546 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-26mb/google/hatch/baseboard: Use chipset devicetree referencesMatt DeVillier
Switch baseboard devicetree to use chipset devicetree references. Drop any devices whose status (on/off/hidden) matches the default in the chipset DT. TEST=build/boot google/hatch (akemi) Change-Id: I5954c304f3c0e04be7e061c1c23a278f81b6ff4d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-26soc/intel/cannonlake: Add/use chipset devicetreesMatt DeVillier
Change-Id: I8ceae832e60cd3094b4a34ab3a279e5a011f2c80 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-26mb/google/hatch/var/helios_diskswap: Use chipset devicetree referencesMatt DeVillier
Switch helios_diskswap overridetree to use chipset devicetree references. Change-Id: I0a3385139c74a59c2006b8963850d00ee39f70a8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78560 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/hatch/var/helios: Use chipset devicetree referencesMatt DeVillier
Switch helios overridetree to use chipset devicetree references. Change-Id: If7901066a0c77231779eb298dc40962d8ac62814 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/hatch/var/hatch: Use chipset devicetree referencesMatt DeVillier
Switch hatch overridetree to use chipset devicetree references. Change-Id: Icccb433ba3e5a1ecb192f8db830674047e801623 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/hatch/var/dratini: Use chipset devicetree referencesMatt DeVillier
Switch dratini overridetree to use chipset devicetree references. Change-Id: I9f365077291ee9fa5f4dcf8835756f4cfd6eeab4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/hatch/var/akemi: Use chipset devicetree referencesMatt DeVillier
Switch akemi overridetree to use chipset devicetree references. Drop USB port overrides which are identical to the baseboard. TEST=build/boot google/hatch (akemi) Change-Id: Ic25fbe4a634f8166047107a33c9fcee764f1159a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78552 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26drivers/intel/gma/Kconfig: Add VBT compression configuration entryJeremy Compostella
Introduce Kconfig choice to pick between lzma, lz4 and no compression at all of the VBT binary. If VBT is needed in romstage, it can be used to set VBT lz4 compression as an alternative to enabling lzma compression support. Indeed, the extra lzma code needed to de-compress VBT undermines the compression size reduction between lzma and lz4. BUG=b:279173035 TEST=Verified that vbt.bin is lz4 compressed with VBT_CBFS_COMPRESSION_LZ4 and not compressed at all with VBT_CBFS_COMPRESSION_NONE Change-Id: I1df6a96c2ec122f0ef8ee6a1e96ffbd621b14941 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/starlabs/*/Kconfig: Fix default power state after failureMatt DeVillier
POWER_STATE_OFF_AFTER_FAILURE can't be directly selected since it's a choice, so instead set POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n, as it's functionally equivalent. This fixes the warnings generated by the pre-commit hook Kconfig check. It is necessary to override and set default n in the mainboard Kconfig as it is set to default y in src/soc/intel/common/block/pmc/Kconfig. TEST=select starlabs/starbook_adl in menuconfig and verify the default power-on setting is S5/soft off. Change-Id: I3ce33517dcc0af693b8db8d1de2926117ad3c16b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78627 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/zork: Add FP enable for MorphiusJon Murphy
Add FP enable/disable based on SKU ID for Morphius. This is meant to resolve a UMA issue with Morphius devices that had the FPMCU populated on non-fp devices. Since the FPMCU is present, and the firmware enables the power GPIO's based on variant, not SKU, the devices were reporting data on fingerprint errantly. BUG=b:258040377 TEST=Flash to Morphius, test FP. Disable test SKU, flash on Morphius, test FP. Change-Id: If5794a9a1b7eb3daaa4cdfd1354dfb0c688624fd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78622 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-26Add Intel maintainers for x86, soc/intel, FSP, ACPIHannah Williams
Change-Id: I67bf98ee7661b031be6d1d77a4db8d816c4a6a0b Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78272 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-26soc/intel/apollolake: Select USE_LEGACY_8254_TIMERSean Rhodes
CB:77409 corrected what the UPD `Timer8254ClkSetting` was set to; this stopped a few boards from booting. Selecting USE_LEGACY_8254_TIMER ensures that the previous behaviour is maintained. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibf898cae6c9fbaf3dc7184eee745278d9b5eade4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78504 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25arch/arm64/cache: Implement helpers to obtain CPU cache detailsBenjamin Doron
This is required for compliant ACPI/SMBIOS implementations on AArch64, and can optionally be displayed to the user. Change-Id: I7022fc3c0035208bc3fdc716fc33f6b78d8e74fc Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-25mb/google/zork: Use device aliases for audio overridesMatt DeVillier
Simplify audio overrides for dalboz baseboard-based variants by using device aliases. This prevents duplicate ACPI devices from being generated for the ChromeEC i2s tunnel (which causes Windows to BSOD with an ACPI_BIOS_ERROR). TEST=build/boot Win11 on google/zork (vilboz), dump ACPI tables and verify only one EC tunnel device in SSDT. Change-Id: I56aa2f761843aa269620f7e8c89ae9c0f205f349 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78509 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25mb/google/zork: Fix audio config on dalboz variantsMatt DeVillier
There is only a single i2c tunnel bus for audio from the EC, so all attached devices need to exist under a single device attached to that bus. This change will facilitate cleanup/simplification using device aliases in a subsequent commit. TEST=tested with rest of patch train Change-Id: Ie09c682a7419868d39421574568dff1a651fa0dc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25soc/amd/stoneyridge: Select SOC_AMD_COMMON_LATE_SMM_LOCKINGMatt DeVillier
Select SOC_AMD_COMMON_LATE_SMM_LOCKING to ensure that SMM remains unlocked on S3 resume until after the AGESA call to s3finalrestore has completed. If SMM is locked prior, S3 resume will fail: [DEBUG] agesawrapper_amds3laterestore() entry [DEBUG] Error: Can't find 57a9e200 raw data to imd [ERROR] S3 volatile data not found TEST=build/boot google/liara, verify S3 resume succeeds. Change-Id: I49659b4e5aba42367d6347e705cd92492fc34a0f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-25soc/amd/common/smm: Add option for late SMM lockingMatt DeVillier
Pre-Zen SoCs like Stoneyridge call into an AGESA binary as part of S3 resume, which will fail if SMM is locked, causing the device to (eventually) cold boot. To mitigate this, add a new Kconfig to enable "late" SMM locking, which restores the previous behavior prior to commit 43ed5d253422 ("cpu/amd: Move locking SMM as part of SMM init"). TEST=tested with rest of patch train Change-Id: I9971814415271a6a107c327523a0a7c188a91df6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78352 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25soc/amd/*/Kconfig: rework SPL optionsFelix Held
Move all security patch level (SPL) related Kconfig options to the common AMD PSP Kconfig file. Commit 4ab1db82bb30 ("soc/amd: rework SPL file override and SPL fusing handling") already reworked the SPL handling, but missed that another Kconfig option SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL controlled if the PSP mailbox command to update the SPL fuses was sent by the code that got added to the build when PERFORM_SPL_FUSING was selected. To make things less unexpected, rename PERFORM_SPL_FUSING to SOC_AMD_COMMON_BLOCK_PSP_SPL since it actually controls if the SPL support code is added to the build and also rename SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL to PERFORM_SPL_FUSING. This changes what PERFORM_SPL_FUSING will do from including the code that could do the fusing if another option is set to being the option that controls if the fusing mailbox command will be set. All SoCs that support SPL now select SOC_AMD_COMMON_BLOCK_PSP_SPL in their Kconfig, which won't burn any SPL fuses. The logic in the Skyrim mainboard Kconfig file is reworked to select PERFORM_SPL_FUSING for all boards on which the SPL fuses should be updated; on Guybrush PERFORM_SPL_FUSING default is changed to y for all variants. The option to include the code that checks the SPL fusing conditions and allows sending the command to update the SPL fuses if the corresponding Kconfig is set doesn't need to be added on the mainboard level, since it's already selected at the SoC level. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12fd8775db66f16fe632674cd67c6af483e8d4e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-25mb/google/kahlee: Alphabetize Kconfig selectionsMatt DeVillier
Change-Id: I72ef272e48db7683a3170e157edd0a782143e8aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-25mb/google/kahlee: Select SOC_AMD_COMMON_BLOCK_GRAPHICS_ACPCoolStar
Select ACP audio for kahlee since it's located on the GPU. TEST: build/boot careena to Win10. Observe audio device shows up Change-Id: I51527a1bfae3e12ce5cf1da8a3465bbc9ddfa76e Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78406 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-25soc/amd/common: Add ACP device to common block graphics driverCoolStar
Supports a brand new ACP driver for STONEY / Grunt chromebooks. AMD's Audio CoProcessor handles i2s/tdm audio, and is located on the GPU. On Windows the PCIe device for the GPU is owned by the AMD proprietary driver, hence a separate device has to be added for the ACP driver. Fortunately since IOMMU is disabled on STONEY, the driver itself can pull BAR5 from the GPU and use that to initialize, so no special configuration is required in ACPI other than the ID. Change-Id: I0e31c3b31fa9fb99578c04b79fce2d8c1d695561 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-25mb/google/rex: Create deku variantEran Mitrani
BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku built without errors. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I332e404e82a7980bb8ed1fb084fe957f526f81d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78393 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-25drivers/elog: Remove NULL check for array created in codeMartin Roth
Checking to see if a the location of a static variable is NULL isn't super useful. If the check ever fails, there are much larger issues. Found-by: Coverity Scan #1452607 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6d3e012542287511f61807075c998efd6d10441e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78614 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25mb/prodrive/hermes: Limit amount of data copied into structMartin Roth
Change strcpy to strncpy just to be safe. Found-by: Coverity Scan #1446759 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7ed094a313692806a6ab6b4226b9978647e9cb8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-10-25mb/prodrive/hermes: Skip NULL check after setting up structMartin Roth
By calling get_board_settings() when board_cfg is initialized, board_cfg is guaranteed not to be NULL, so don't check to see if it's NULL. Found-by: Coverity Scan #1513079 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I61105be9ed71ff30efdda66d2cbfcaf54d70053f Reviewed-on: https://review.coreboot.org/c/coreboot/+/78618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-10-25mb/hp/280_g2/devicetree: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the devicetree at their related root ports. Change-Id: I85f7c0ddebf88dd21e6c2603ce45f0a4fc868d51 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78600 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25mb/kontron/bsl6/devicetree: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the devicetree at their related root ports. While on it, remove superfluous comments related to modified settings. Change-Id: I67f4fdcfb59da6c594c89d7ad3ee7f2ddbbea69b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78592 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25mb/asrock/h110m/devicetree: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the devicetree at their related root ports. Change-Id: I25b87a157e934640355442edceb0760827dc7a43 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78591 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25mb/facebook/monolith/devicetree: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they will be moved into the devicetree to their related root ports at some later point. While on it, remove superfluous comments related to modified settings. Change-Id: I19af8c6b1167af793eb18b000fd93ec409385587 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78597 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2023-10-25devicetrees: Remove trailing backslash from multiline valuesFelix Singer
It's not needed to put a backslash at the end of a line for quoted multiline values. Thus, remove it. Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-25device/dram/ddr3.c: Check SPD byte before using as a divisorMartin Roth
The Medium Time Base (MTB) value is calculated by dividing one SPD byte by another. Return an error if the divisor is zero before using the value for division. Found-by: Coverity Scan #1469303 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic0a70291c42b5c2d21d65de92487b2dd88609983 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78613 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-25include/device/dram: Add SPD lengths for DDR3 to DDR5Martin Roth
DDR2 already had a define to specify the SPD length, but other memory types did not. This led to the value being coded into other locations. Unify the definition for DDR2 to DDR5 and put the value at the top of the respective header file. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id13b9c5d311984d4a98b831a8746d1659724aa96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-25SNB+MRC boards: Migrate MRC settings to devicetreeKeith Hui
For Sandy Bridge boards with MRC raminit support, migrate as much MRC settings to devicetree as possible, to stop mainboard code from needlessly overwriting entire PEI data structure, so they will not interfere with upcoming transition to one standard Haswell way of providing SPD info to northbridge. Some exceptions allowed are described below and in code comments. SPD-related items are kept out of devicetree for now. They will be migrated (with a different representation) with the Haswell SPD transition. google/{butterfly,link,parrot,stout} have max DDR3 frequency set in pei_data to 1600 (2*800), but in devicetree to 666. The reason for the difference seems to be problems with native raminit code. These are converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an added "fix me" tag. asus/p8x7x-series also needs the same treatment, based on testing various memory on p8z77-m hardware. TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested. Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-25cbmem.h: Drop cbmem_possible_online in favor of ENV_HAS_CBMEMArthur Heymans
The macro ENV_HAS_CBMEM achieves the same as this inline function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6d65ca51c863abe2106f794398ddd7d7d9ac4b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77166 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2023-10-24soc/intel/meteorlake: Add PsysPmax configurationJakub Czapiga
psys_pmax_watts is configured in SoC node of devicetree. Value represents Watts the PSU provides. Zero means automatic/default configuration (not optimal). BUG=b:289853442 TEST=Build google/rex/ovis4es target board Change-Id: I69afa06110254f6384352c062891c0c9c0b23070 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76796 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-24mb/google/skyrim/var/crystaldrift: Update the STT settingsYunlong Jia
Adjust the STT settings. BRANCH=none BUG=b:270112575 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1df9bbf820b5a760007dcfd7bceb21063fc24696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78523 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-10-24mb/google/zork: Use device aliases in device/overridetreesMatt DeVillier
Replace all remaining numeric references to PCI devices with their aliases in chipset.cb. Change-Id: I636f04c06c250639867c770511095773cb0c5205 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-24Update amd_blobs submodule to upstream main branchMatt DeVillier
Updating from commit id b1741d184add (2023-10-04): PCO: Update SMU firmware to 4.30.77.200 to commit id edd465837e26 (2023-10-20): cezanne: Update PSP binaries to release 0.11.11.75 This brings in 4 new commits: edd465837e cezanne: Update PSP binaries to release 0.11.11.75 480c9d2efd picasso: Update PSP binaries to release 0.8.13.7B 1b1fd40889 Stoneyridge: Update SMU firmware for fanless/kicker to 33.10.0 c99172d385 Stoneyridge: Update SMU firmware to 26.17.0 Change-Id: I1fc1756a204e5f637ca67ef51daf4592572a6a17 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-10-24soc/amd/stoneyridge: Update SMU fw2 name in fw.cfgMatt DeVillier
Update the filename for the PSP_SMUFW2_SUB1_FILE to use the compressed and signed version (.csbin) rather than the uncompression + signed version (.sbin), in order to be consistent with the other SMU firmware files. This will also facilitate dropping the duplicate files in an upcoming update to the amd_blobs repo and updating the SMU files (all of which are .csbin). This change is actually a no-op since the .csbin and .sbin are the same file; it appears that the .sbin file was incorrectly named when added, and then the same file was added later with the correct extension. TEST=build/boot google/kahlee (liara) Change-Id: I10fa8e949ab589d315862c06b4125c902520cbbc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-24mb/google/kahlee: Enable display backlight control in WindowsCoolStar
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF to provide the Windows driver with information on backlight settings. TEST: Boot google/careena to Win10. Observe display brightness controls functional after driver loads (immediately with patched driver, 30 minutes with unpatched). Change-Id: I6792a91f26a5f6e4dc478cdde776ff749f08946f Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78429 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-24soc/amd/stoneyridge: Use common block graphics driverCoolStar
Select the common block graphics driver for Stoneyridge. Drop Stoney's ACPI stub for the iGPU as the device will now be generated by the common block acpigen and put into the SSDT. TEST=tested with rest of patch train Change-Id: I260b964be59c1a208ff907c474243a9ace03f206 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78428 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-24soc/amd/common/graphics: Factor out FSP graphics initMatt DeVillier
Factor out the FSP-dependent graphics init call and header into a separate file, so that the common graphics init can be used by non-FSP platforms (eg Stoneyridge) without any preprocessor guards. TEST=build google/skyrim Change-Id: Ib025ad3adec0945b4454892d78c30b4cc79e57a0 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78599 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-24ec/starlabs/merlin/ite: Adjust the mirror flag handlingSean Rhodes
In EC versions older than 1.18, if the mirror flag was enabled, the EC would mirror once the system reached S5. When a mirror is successful, the system will automatically power on, as it acts like it's been in G3. This led to machines turning on when the intention was them to be off. In 1.18 and later, they're installed when turning on. The result was slower boot times when mirroring, but no unwanted powering on. Because of this, coreboot no longer needs to power off when setting the mirror flag. Change-Id: I973c1ecd59f32d3353ca392769b44aadf5fcc9c3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-24mb/starlabs/starbook/{adl,rpl}: Disable GpioOverrideSean Rhodes
Disable the GpioOverride UPD in FSP M, and comment out the Clock Request GPIOs to ensure that coreboot doesn't touch them. This solves behaviour that can only be described as weird: * Devices connected to Root Ports don't initialise * Hang seen when entering S5 * Hang when edk2 is reached Change-Id: Idf8d2112a1c44064af73bb54fd3e1a1a429e0649 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-24mb/google/hatch: Default native SD card interface to off in baseboardMatt DeVillier
Default SD card interface (PCI 14.5) to off in the baseboard, and have all variants which use it enable it in their override tree. This will allow for simplification when moving to using the chipset devicetree references in a later patch. Change-Id: I6e1230045f54e0fee376f5eeeca9da4fb9d5f6c4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
2023-10-24mb/google/hatch: Default I2C3 (proximity sensor) to off in baseboardMatt DeVillier
Default I2C3 (proximity sensor) to off in baseboard, since all variants which use one already enable it in their override tree. This allows variants which do not use it (the majority) to drop it from their override trees. Change-Id: If17cb4538a7f64d019e4e28285fb8977de72252f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
2023-10-24mb/google/hatch: Default I2C2 (digitizer) to off in baseboardMatt DeVillier
Default I2C2 (digitizer) to off in the baseboard, since all variants which use one already enable it in their override tree. This allows variants which do not use it (the majority) to drop it from their override trees. Change-Id: Ife42a6b849278362c1951b80b7a95363e68a2541 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78548 Reviewed-by: Yuchen He <yuchenhe126@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-24mb/google/hatch: Default GSPI1 (FPR) to off in baseboardMatt DeVillier
Default GSPI1 (fingerprint reader) to off in baseboard, since all variants which use one already enable it in their override tree. This allows variants which do not use it to drop it from their override trees. Change-Id: I07979e35b67635ceadd3906e37de177dd081d35a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78547 Reviewed-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-24drivers/wwan/fm: Wake up modem on PEWAKE# signal changePaweł Anikiel
Create an event handler for the PEWAKE# GPIO and notify the device driver to wake up the device. BUG=b:301150499 TEST=Compiled and tested on google/redrix: 1. Enable runtime suspend for linux mtk_t7xx driver 2. Wait for device to enter suspended state 3. Modem should be able to wake up driver, e.g. on SIM card insert/eject The interrupts should show up under /proc/interrupts as ACPI:Event Signed-off-by: Paweł Anikiel <panikiel@google.com> Change-Id: I32257689da85ea71f9de781093b3ede0cfe70a0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78297 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-24mb/google/brya: Set WWAN_PCIE_WAKE_ODL as interrupt on RedrixPaweł Anikiel
This signal gets deasserted by the WWAN modem to reactivate the PCIe link when in low power mode. In order to handle this efficiently, the kernel needs to set up an interrupt. BUG=b:301150499 TEST=Compiled and tested on google/redrix Signed-off-by: Paweł Anikiel <panikiel@google.com> Change-Id: I37f6836aefe4a374eaff3e4bc11358be274cf563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78416 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-23soc/intel/cannonlake: Add ACPI devices for FSPI, SRAM, HEC1Matt DeVillier
Add ACPI devices for these components so that generated LPI constraints for them have valid device references. TEST=tested with rest of patch train Change-Id: I3b85fec3de8f33d338425a417cc8b0f5290a5e4f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78520 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-23soc/intel/tigerlake: Add ACPI devices for FSPI, SRAM, HEC1Matt DeVillier
Add ACPI devices for these components so that generated LPI constraints for them have valid device references. TEST=tested with rest of patch train Change-Id: Ib70dc29f54d28ec1fe7b630ab3fab24bcdd08154 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78519 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23soc/intel/common/acpi: Don't generate LPI constraints for disabled/hidden ↵Matt DeVillier
devices When walking the devicetree to generate the list of devices and minimum sleep states, skip any devices which have the disable or hidden flags set. This prevents adding entries for devices which are not present, which are hidden (and likely to not have a min sleep state entry), or generating duplicate entries in the case of PCIe remapping. Any of these conditions are considered invalid by Windows and will result in a BSOD with an INTERNAL_POWER_ERROR. TEST=tested with rest of patch train Change-Id: I06f64a72c82b9e03dc8af18700d24b3d10b7d3a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-23soc/intel/common/pcie: Disable removed RPs when updating devicetreeMatt DeVillier
If a root port is not present but was enabled in the devicetree, mark it disabled so that no ACPI references will be generated by any function which walks the devicetree (eg, LPI constraints). TEST=tested with rest of patch train Change-Id: I52e23fb1c0148a599ed736fc294e593ebbd27860 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78517 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23util/docker/coreboot-sdk: Add bash-completion to package listFelix Singer
Change-Id: I97756f603e304c6b50387ba2aaac416ae31db681 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-23mb/system76/rpl: Fix bonw15, oryp11 speaker outputLevi Portenier
Users have reported audio cutting in and out when playing through the speakers on bonw15 and oryp11. This issue originally only affected serw13 and was fixed before upstreaming. Apply the updated HDA verb provided by Clevo to fix speaker output on these units as well. Change-Id: I105bf165227456593863faa9bb8c4f152e49796b Signed-off-by: Levi Portenier <levi@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Daniel Sutton <daniel@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-10-23mb/google/brya/variants/anraggar: Generate 13 RAM IDswuweimin
Vendor DRAM Part Name Type MICRON MT62F512M32D2DR-031 WT:B LPD5 HYNIX H9JCNNNBK3MLYR-N6E LPD5 HYNIX H9JCNNNCP3MLYR-N6E LPD5 MICRON MT62F1G32D4DR-031 WT:B LPD5 HYNIX H9JCNNNFA5MLYR-N6E LPD5 MICRON MT62F2G32D8DR-031 WT:B LPD5 SAMSUNG K3KL6L60GM-MGCT LPD5x MICRON MT62F1G32D2DS-026 WT:B LPD5x SAMSUNG K3KL8L80CM-MGCT LPD5x HYNIX H58G56BK7BX068 LPD5x MICRON MT62F2G32D4DS-026 WT:B LPD5x SAMSUNG K3KL9L90CM-MGCT LPD5x HYNIX H58G66BK7BX067 LPD5x BUG=b:304920262 TEST=Run part_id_gen tool without any errors Change-Id: I2968c2f0b9cdd55235f9833a3d3cdb3c83b8601b Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-23mb/google/rex/var/karis: Modify TCC_offset to 10Tyler Wang
Follow thermal team request, modify tcc_offset from 20 to 10. BUG=b:306548525 TEST=Build and verified by thermal team Change-Id: I7537e103be4cd1196c934ca72dbd61e064aed371 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-10-23mb/google/dedede: Add HPD GPIOs on dexi variantKenneth Chan
Some Type-C monitors do not immediately assert HPD. If we enter FSP-S before HDP is asserted, display initialisation may fail. So wait for HPD. This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP output on cold boots") on puff, except we don't use google_chromeec_wait_for_displayport() since that EC command was removed for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if HDMI is connected, which is the same behaviour as puff and fizz. BUG=b:303533815 BRANCH=dedede TEST=On dexi, connect a display via a Type-C to HDMI dongle and check the dev and recovery screens are now displayed correctly. Also check the logs in the following cases: Cold reboot in dev mode, Type-C to HDMI dongle: HPD ready after 800 ms Warm reboot in dev mode, Type-C to HDMI dongle: HPD ready after 0 ms Cold/warm reboot in dev mode, direct Type-C: HPD ready after 0 ms Cold/warm reboot in dev mode, direct HDMI: HPD ready after 0 ms Cold/warm reboot in dev mode, no display: HPD not ready after 3000 ms. Abort. Change-Id: Ib4fc071cac98a542072ffbeb6943bff4c988554c Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78450 Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/brya/var/dochi: Update overridetree for FingerPrintMorris Hsu
Update overridetree to correct FP_MCU fw_config settings. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: If76dd8fa3567ed01b11a6d2ba796e8c39807816c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78454 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/brya/var/dochi: Update overridetree for TouchPadMorris Hsu
Update overridetree for TouchPad. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I4f88fa8a34b65aaeb64746e7f02e82d9913ce21b Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78455 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/nissa/var/gothrax: Supplement register settings for SX9324 P-sensorYunlong Jia
Set the following register value to make SX9324 work normally "ph0_pin" = "{1, 3, 3}" "ph1_pin" = "{3, 2, 1}" "ph2_pin" = "{3, 3, 1}" "ph3_pin" = "{1, 3, 3}" "ph01_resolution" = "512" "ph23_resolution" = "1024" "startup_sensor" = "1" "ph01_proxraw_strength" = "2" "ph23_proxraw_strength" = "2" "avg_pos_strength" = "256" "cs_idle_sleep" = ""gnd"" "int_comp_resistor" = ""lowest"" "input_precharge_resistor_ohms" = "4000" "input_analog_gain" = "3" BUG=b:295109511 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage & Check sar sensor data Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib15f12d754fec8b379afd702b27d0701fac78072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-23drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resumeBill XIE
After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1"), Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via bisect). Further inspection shows that DRAM training result of GM45 is stored in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume to restore, but it will be erased by sanitize_cmos(), which now clears both bank 0 and bank 1, leaving only "untrained" result restored, so s3 resume will fail. However, resetting CMOS seems unnecessary during s3 resume. Now, cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true. Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again with these changes. Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/rex: Use upstream driver properties for SX9324Ivy Jian
Use human readable properties as upstream driver support. BUG=b:297977526 TEST=Able to get sensor values changed w/wo a hand covering the device. before this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { Zero, Zero, Zero }, ... Package (0x02) { "semtech,ph23-resolution", Zero }, Package (0x02) { "semtech,startup-sensor", Zero }, .... after this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { One, 0x02, 0x02 }, ... Package (0x02) { " semtech,ph23-resolution", 0x0400 }, Package (0x02) { "semtech,startup-sensor", One }, Change-Id: Ie0d929228f4510f33b07d9c4cfdfcd2a9a437c27 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78174 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
2023-10-23mb/system76: Enable BayHub driver for all TGL+Tim Crawford
Clevo had apparently swapped the Realtek card reader for the O2 Micro card reader for newer batches of all TGL models. Enable the BayHub driver on everything (except bonw15, which doesn't have a card reader) to fix LTR programming, as was done for other in commit 3d7a5bdf58e0 ("mb/system76: Enable DRIVERS_GENERIC_BAYHUB_LV2 to fix LTR issue"). Tested on system76/galp5: CPU reaches C-states deeper than C2 when idle. Change-Id: I3667e08acd23c12638159a2f7d2592737a34e63d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-23mb/google/dedede/var/cret: Modify Goodix touchpad HIDDtrain Hsu
Update Goodix touchpad HID to GDIX0000 for GXTP7288 and GXTP7863. BUG=b:305118852 BRANCH=firmware-dedede-13606.B TEST=Build and touchpads are workable # evtest for GXTP7863 No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: Elan Touchscreen /dev/input/event5: GDIX0000:00 27C6:0D51 Mouse /dev/input/event6: GDIX0000:00 27C6:0D51 Touchpad # evtest for GXTP7288 No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event10: GDIX0000:00 27C6:01F5 Touchpad /dev/input/event11: sof-da7219max98360a Headset Jack /dev/input/event12: sof-da7219max98360a HDMI/DP,pcm=2 /dev/input/event13: sof-da7219max98360a HDMI/DP,pcm=3 /dev/input/event14: sof-da7219max98360a HDMI/DP,pcm=4 /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: ELAN900C:00 04F3:2E5D /dev/input/event5: ELAN900C:00 04F3:2E5D UNKNOWN /dev/input/event6: ELAN900C:00 04F3:2E5D UNKNOWN /dev/input/event7: ELAN900C:00 04F3:2E5D Stylus /dev/input/event8: ELAN900C:00 04F3:2E5D Stylus /dev/input/event9: GDIX0000:00 27C6:01F5 Mouse Change-Id: Id2a6223bdbb2f0693149136baa853ca2efb57815 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20soc/amd/*: Set AMD_FW_AB_POSITION to either 64 or 128 bytesKarthikeyan Ramasubramanian
When CBFS verification is enabled, add amdfw_a/b.rom at offset 128 bytes to account for CBFS file header with hash attribute. When CBFS verification is disabled, add amdfw_a/b.rom at offset 64 bytes to account for CBFS file header without hash attribute. BUG=None TEST=Build Skyrim, Myst BIOS images with and without CBFS verification enabled. Change-Id: Ic374ac41df0c8fb8ce59488881ce5846e9058915 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-20soc/amd/phoenix/psp_verstage: Fix the hash file namesKarthikeyan Ramasubramanian
Fix the hash file names to be used to verify signed PSP binaries when booting with VBOOT FW Slot B. BUG=None TEST=Build and boot to OS in Myst with PSP Verstage enabled using both VBOOT slots A and B. Change-Id: I89f02922bc901d8ac71d48bf5128fe6ecead43a0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-20mb/google/myst: Enable CBFS VerificationKarthikeyan Ramasubramanian
Enable RO verification by GSC and RO/RW CBFS verification. BUG=b:277087492 TEST=Build and boot to OS in Myst with CBFS verification enabled using PSP verstage. Change-Id: I2dd3ce59f331f89660185309ccf60c53d50e4fad Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78235 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20soc/amd/phoenix: Disable CCP DMA in PSP VerstageKarthikeyan Ramasubramanian
Some stalls are observed while using CCP DMA in PSP verstage - especially with CBFS verification enabled. Also with RW CBFS verification enabled, the entire firmware body is not loaded during verstage for verification. Instead the files are verified as and when they are loaded from CBFS. Hence the impact to boot time is reduced since only few files are loaded during PSP verstage. Hence disable CCP DMA in PSP verstage until the root cause is identified. BUG=None TEST=Build and boot to OS in Myst with CBFS verification enabled. Change-Id: I22ac108b08abcfe432dfd175644393e384888e11 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78234 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20soc/amd/phoenix: Add build rules to enable CBFS verificationKarthikeyan Ramasubramanian
Add SPI flash RO ranges to be verified by GSC in order to enable CBFS verification. Also with CBFS verification enabled, CBFS metadata is more than 64 bytes. So configure the offset of amdfw_a/b to 128 bytes - next address aligned to 64 bytes. BUG=b:277087492 TEST=Build and boot to OS in Myst with and without CBFS verification enabled. Change-Id: Ibfffd3d6fce8b80ec156a7b13b387e1df8c43347 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78233 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20soc/intel/meteorlake: Set build time physical address reserved bitsJeremy Compostella
Meteor Lake TME bits [42-45] are reserved regardless of if the part supports TME or not. On a device with TME fused off, we noticed some reboot hangs which have been narrowed down to internal IP routing issues when the IA accesses the Input Output Manager (IOM) which is mapped at 0x3fff0aa0000 (0x3ff upper 32 bits). It turns out since TME is fused off, coreboot uses the full physical address size reported by CPUID MAXPHYADDR (46 bits). Therefore, it allocates thunderbolt memory range on 46 bits (0x3fff upper 32 bits). Since 4 of these bits are actually reserved, it seems that this address range is "stripped down" to 42 bits (=> 0x3ff upper 32 bits) resulting in potential conflict with other devices such as IOM. BUG=b:288978352 TEST=No reboot issue on rex with TME fused off Change-Id: I96ba23ab304257003c0413243d3ac8129ce31743 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78452 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20cpu/intel/common: Define build time physical address reserved bitsJeremy Compostella
According the Intel Software Developer Manual, CPUID.80000008H:EAX[15:8] reports the physical-address width supported by the processor. Unfortunately, it does not necessarily reflect the physical-address space the system can actulally use as some of those bits can be reserved for internal hardware use. It is critical for coreboot to know the actual physical address size. Overestimating this size can lead to device resource overlaps due to the hardware ignoring upper reserved bits. On rex for instance, it creates some reboot hangs due to an overlap between thunderbolt and Input Output Manager (IOM) address space. As some SoCs, such as Meteor Lake, have physical address reserved bits which cannot be probed at runtime, this commit introduces `CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS' Kconfig to set the number of physical address reserved bits at compilation time for those SoCs. A runtime detection by hardware probing will be attempted if the value is 0 (default). BUG=b:288978352 Change-Id: I8748fa3e5bdfd339e973d562c5a201d5616f813e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78451 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-20Revert "mb/google/rex: Enable sending EOP from payload"Matt DeVillier
This reverts commit 55b7dee2784e9fe80870c6c33ba91b98021df8b5. Reason for revert: accidentally submitted out of order / breaks tree Change-Id: Ic15d0e3688cd54f7d678998341263e7bd30e75f2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78525 Tested-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-20Revert "ec/dell/mec5035: Hook up radio enables to option API"Matt DeVillier
This reverts commit bb5fa6419dfd71950e61e75eecd48ef8203bb1b1. Reason for revert: accidentally committed out of order; reverting to unbreak tree Change-Id: I36aa1fd3a0befe49b7e9e34198676f16fb08cf73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78524 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: Martin L Roth <gaumless@gmail.com>
2023-10-20ec/dell/mec5035: Hook up radio enables to option APINicholas Chin
Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-20x86: Add ramstage CBFS cache scratchpad supportJeremy Compostella
Having a CBFS cache scratchpad offers a generic way to decompress CBFS files through the cbfs_map() function without having to reserve a per-file specific memory region. This commit introduces the x86 `RAMSTAGE_CBFS_CACHE_SIZE' Kconfig to set a ramstage CBFS cache size. A cache size of zero disables the CBFS cache feature. The default size is 16 KB which seems a reasonable minimal value large enough to satisfy basic needs such as the decompression of a small configuration file. This setting can be adjusted depending on the platform needs and capabilities. To support S3 suspend/resume use-case, the CBFS cache memory cannot be released to the operating system. There are two options to meet this requirement: 1. Define a static CBFS cache buffer (located in the .bss section) 2. Create a new CBMEM entry Option #2 seems more powerful but considering that: 1. The CBFS cache is actually not a cache but just a scratch pad designed to be isolated between stages 2. postcar is a very short stage not really needing CBFS cache 3. The static initialization of the `cbfs_cache' global variable (cf. src/lib/cbfs.c) offers a simple and robust design => It is simpler to use a static buffer and limit the support to ramstage. Since some AMD SoCs (cf. `SOC_AMD_COMMON_BLOCK_NONCAR' Kconfig) define a `_cbfs_cache' region, an extra `POSTRAM_CBFS_CACHE_IN_BSS' Kconfig must be set to enable the use of a static buffer as the CBFS cache scratchpad. TEST=Decompression of vbt.bin in ramstage on rex using cbfs_map() Change-Id: I7fbb1b51cda9f84842992e365b16c5ced1010b89 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77885 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20x86: Add pre-memory stages CBFS cache scratchpad supportJeremy Compostella
Having a CBFS cache scratchpad offers a generic way to decompress CBFS files through the cbfs_map() function without having to reserve a per-file specific memory region. This commit introduces the x86 `PRERAM_CBFS_CACHE_SIZE' Kconfig to set the pre-memory stages CBFS cache size. A cache size of zero disables the CBFS cache feature. The default value is 16 KB which seems a reasonable minimal value enough to satisfy basic needs such as the decompression of a small configuration file. This setting can be adjusted depending on the platform needs and capabilities. We have set this size to zero for all the platforms without enough space in Cache-As-RAM to accommodate the default size. TEST=Decompression of vbt.bin in romstage on rex using cbfs_map() Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-10-20cbfstool: Skip relocation entries pointing to undefined symbolJeremy Compostella
The linker can make relocation entries of a symbol which has a value of zero point to the undefined symbol entry. It is permitted since when the symbol value is zero as the documentation of the relocation entry `r_info' field states: "If the index is STN_UNDEF, the undefined symbol index, the relocation uses 0 as the symbol value." The ELF binary does not really have any missing symbols. It is an optimization as the symbol points to the undefined symbol because its value is zero. A typical way to hit this cbfstool limitation is to define an empty region using the REGION macro in the linker script. Here is an example if we assume `CONFIG_MY_REGION' is set to 0: .car.data { [...] REGION(my_region, CONFIG_MY_REGION_SIZE) [...] } A region is defined as follow: #define REGION_SIZE(name) ((size_t)_##name##_size) #define DECLARE_REGION(name) \ extern u8 _##name[]; \ extern u8 _e##name[]; \ extern u8 _##name##_size[]; So the size of the region is actually the address of the `_##name##_size' symbol. Therefore, the `_my_region_size' symbol address is zero and the linker can make the relocation entry of this symbol point to the undefined symbol index. In such a situation, cbfstool hits a segmentation fault when it attempts to relocate the symbol in `parse_elf_to_xip_stage()' function. We resolves this issue by making cbfstool skips relocation entries pointing to the undefined symbol similarly to the way it skips relocation relative to absolute symbols. A symbol which value is zero can be considered an absolute symbol and therefore should not be relocated. Of course, we could argue that we could just prevent the declaration of an empty region as illustrated in the following example: .car.data { [...] #if CONFIG_MY_REGION_SIZE > 0 REGION(my_region, CONFIG_MY_REGION_SIZE) #endif [...] } However, this is not a satisfying solution because: 1. It requires to add unnecessary code in the linker script as an empty region is a valid declaration. Such a workaround requires the code using it to mark the region symbols as weak symbols to handle the situation where the region is not defined. 2. There could be other situations which have yet to be uncovered which would lead the same cbfstool crash. 3. A binary with an empty region is a valid ELF file and cbfstool should not crash when it is asked to create an eXecute-In-Place stage out of it. Change-Id: I2803fd3e96e7ff7a0b22d72d50bfbce7acaeb941 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-10-20soc/cavium/cn81xx/bootblock_custom.S: Specify archArthur Heymans
This fixes assembling with clang which complains about fpu instructions. TEST: BUILD_TIMELESS=1 remains the same. Change-Id: I175b8e749fafde5fb7ffb8101fc0dc892d9b4e0d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74539 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20mb/google/rex: Enable sending EOP from payloadKapil Porwal
Enable sending EOP from payload BUG=b:279184514 TEST=Verify sending EOP from depthcharge on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5eda0a5c6d4c34cfcc2de898adde0b005d6edc1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74768 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20mb/google/brya/var/dochi: Enable EC keyboard backlightMorris Hsu
Enable EC keyboard backlight for dochi. BUG=b:299284564 TEST=FW_NAME=dochi emerge-brya coreboot chromeos-bootimage Change-Id: I1b640c576fcdd368110b88cba6f969f10dfc15f1 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20soc/amd/genoa: Add Global NVSVarshit Pandya
Change-Id: I8d64236fc81e848503535db6f52e93328a60404c Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-20soc/amd/genoa: Hook up IOMMU opsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I2419feed1a76ec1cb04cb9640689b8758fa1d3f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-20soc/amd/genoa: Add SMU header file and SMU KconfigVarshit Pandya
Change-Id: Ief56bff2a1b8825d6e65aeb5f7ed9e8f432e465b Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-10-20soc/amd/genoa: Hook up LPC opsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I068fcbbcb0641cddce8fa85e2a64ab44d91d6bcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/76526 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20soc/amd/genoa: Add MAX_CPUSVarshit Pandya
As per PPR, Genoa supports up to 96 core, that is 192 threads. It also supports dual socket. Change-Id: I817fea7c41477f476794e9e5c16451037d01f912 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-20mb/google/rex/var/karis: Remove I2C2 "on" settingsTyler Wang
GPP_H04/GPP_H05 doesn't use for I2C usage, remove I2C2 "on" settings. BUG=b:294155897 TEST=Check ap firmware log, i2c2 is disabled Change-Id: I0124fd108fbbd87507d252e9caab4dfc16aceddb Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78339 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20mb/google/rex: Set frequency and gears for SaGv pointsBora Guvendik
Update SaGv gears and frequency values as per recommendation from power and performance team. This change doesn't cause negative impact on firmware boot time performance. BUG=b:274137879 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ie8a81c05f25b1cdab1008d09c606d1debea6e6e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-20soc/amd/common/psp_verstage: Add PSP_VERSTACK_STACK_IS_MAPPED configKarthikeyan Ramasubramanian
Crypto Engine in PSP prefers the buffer from Static RAM (SRAM). Hence if a buffer comes from within SRAM address range, then it is passed directly to Crypto Engine. Otherwise a bounce bufer from the stack is used. But on SoCs like Picasso where PSP Verstage stack is mapped to a virtual address space this check fails causing a bounce buffer to be used and hence a stack overflow. Fix this issue by assuming that the buffer comes from the SRAM always in such SoCs and pass the buffer directly to crypto engine. BUG=b:259649666 TEST=Build and boot to OS in Dalboz with unsigned PSP verstage. Change-Id: I2161c8f0720c770efa5c05aece9584c3cbe7712a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-10-20drivers/generic/bayhub: Add ACPI for BH720CoolStar
The Bayhub BH720 eMMC bridge is a fixed internal device, and needs to me marked as non-removable in order for Windows to properly recognize/ utilize the device. Add the necessary ACPI to be generated at runtime. TEST=build/boot/install Win11 on google/kahlee (liara) Change-Id: I0815abf1d2dc5cfe785dc04670ab91f2a6a1af23 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20mb/google/kahlee: Hide Linux machine audio devices from WindowsCoolStar
Windows does not use these devices for audio. Hide these so they don't clutter device manager. Change-Id: Ic85eff7f7ff68e25cc005bbb822bf99374c96532 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78418 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20device/device.h: Rename pci_domain_scan_busArthur Heymans
On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-10-20acpi: Reserve hardware ID for custom AMD ACP driverCoolStar
AMD Audio CoProcessor handles I2S audio on AMD SoC's. Prior to AMD Ryzen platforms (e.g. STONEY) it is located on the Integrated GFX device. As the proprietary AMD driver does not support accessing this easily, reserve a custom ACPI ID from the coreboot namespace so that another driver can be attached in Windows device manager. Change-Id: I855b81908ed9ad0587b6367b052c726c36350208 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>