diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2023-10-22 12:10:35 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-10-26 18:35:57 +0000 |
| commit | b9165199c32ace5d661d28b5afb500b5451efc9b (patch) | |
| tree | f2fa2c34ed35264849996a0f7a30b59ce1bb18e7 | |
| parent | 14701fb6a6ee2e6650961a52d0b68201a556503d (diff) | |
mb/prodrive/hermes: Rework UART devicetree entry
Rework the UART devicetree entry so that it doesn't conflict with the
to-be-added chipset devicetree for CNL. This should be functionally
equivalent to the previous entry, but needs testing to verify.
Change-Id: Iae60cb8e0746e7dc2928da3687762b81928fb5f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78546
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
| -rw-r--r-- | src/mainboard/prodrive/hermes/devicetree.cb | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 8c2dbda38e..024b97d02b 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -170,11 +170,12 @@ chip soc/intel/cannonlake # This device does not have any function on CNP-H, but it needs # to be here so that the resource allocator is aware of UART 2. device pci 19.0 hidden end - chip soc/intel/common/block/uart - device pci 19.2 hidden + device pci 19.2 hidden + chip soc/intel/common/block/uart register "devid" = "PCI_DID_INTEL_CNP_H_UART2" - end # UART #2, in ACPI mode - end + device generic 0 hidden end + end + end # UART #2, in ACPI mode device pci 1b.4 on # PCIe root port 21 (Slot 1) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" register "PcieRpEnable[20]" = "1" |