diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-10-23 08:23:05 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-25 14:18:06 +0000 |
| commit | c4b846f22ab84a9c43b10cca53c78a9c0c8016d5 (patch) | |
| tree | 8109adcabf89acdd9855c11f5cdc812b560ec4e7 | |
| parent | 3b01dd11cbe531b8ae0d34a2c994bd138601ed32 (diff) | |
mb/asrock/h110m/devicetree: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the devicetree at their related root ports.
Change-Id: I25b87a157e934640355442edceb0760827dc7a43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78591
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/asrock/h110m/devicetree.cb | 53 |
1 files changed, 28 insertions, 25 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index f676c5f43e..1e74f0c7c8 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -63,31 +63,34 @@ chip soc/intel/skylake device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), + [1] = USB2_PORT_MID(OC0), + [2] = USB2_PORT_MID(OC4), + [3] = USB2_PORT_MID(OC4), + [4] = USB2_PORT_MID(OC2), + [5] = USB2_PORT_MID(OC2), + [6] = USB2_PORT_MID(OC0), + [7] = USB2_PORT_MID(OC0), + [8] = USB2_PORT_MID(OC0), + [9] = USB2_PORT_MID(OC0), + [10] = USB2_PORT_MID(OC1), + [11] = USB2_PORT_MID(OC1), + [12] = USB2_PORT_MID(OC_SKIP), + [13] = USB2_PORT_MID(OC_SKIP), + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), + [1] = USB3_PORT_DEFAULT(OC0), + [2] = USB3_PORT_DEFAULT(OC3), + [3] = USB3_PORT_DEFAULT(OC3), + [4] = USB3_PORT_DEFAULT(OC1), + [5] = USB3_PORT_DEFAULT(OC1), + [6] = USB3_PORT_DEFAULT(OC_SKIP), + [7] = USB3_PORT_DEFAULT(OC_SKIP), + [8] = USB3_PORT_DEFAULT(OC_SKIP), + [9] = USB3_PORT_DEFAULT(OC_SKIP), + }" end device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on # Thermal Subsystem |