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2021-02-03soc/intel: Fix compilation on x86_64Patrick Rudolph
Change-Id: I18a0c18fe1c64611f95bc423916447c89585db9f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-02-02soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI codeFelix Held
commit 3f2467032e3e40cd456d2d9fe5120a60283784aa changed this in the APCI code itself, but the change in the ACPI byte code generation in pcie_gpp.c was missed and this patch fixes that. TEST=Fixes the regression on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I60de29581296101947336f70343d6206af97e307 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-02soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE definesFelix Held
This define was copied over from Stoneyridge, but isn't present on Picasso and newer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-02tests: Add lib/region_file-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ic48e52a97b18d55fd983315f25dc972f472cc473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-02mb/siemens/mc_apl1: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49442 Tested-by: siemens-bot Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02soc/intel/baytrail,braswell: Drop TOLM from GNVSKyösti Mälkki
It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50121 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-02soc/intel/baytrail,braswell: Sync PCI memory region in ASLKyösti Mälkki
Baytrail had (only) occurence of DwordMemory vs DWordMemory. Braswell one had bogus comments about the PCI memory range. The actual region details are dynamically filled in _CRS. Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02treewide [Kconfig]: Remove useless commentElyes HAOUAS
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01soc/amd/common: Use only byte access for old GPIOKyösti Mälkki
Change-Id: I06ec29845d051d9b90ab6f3cfb269ad5e6b75ea8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-01soc/amd/picasso/fch.c: Remove unused <acpi/acpi_pm.h>Elyes HAOUAS
Change-Id: I5fea31f5893227a3e076c83a1759d3795b68c943 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-01soc/amd/common: Drop ACPIMMIO GPIO bank separationKyösti Mälkki
It's assumed in ASL already that the banks appear one after other in ACPIMMIO space. There is no need for the separation of accessor functions by name. Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-01mb/pcengines/apu2: Switch to proper GPIO APIKyösti Mälkki
Use the abstractions <gpio.h> provides. Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-01soc/intel/broadwell/gma.c: Add missing `break` in switchAngel Pons
Otherwise, the `GT_CDCLK_675` case falls through and exits early. Change-Id: Icb979f8a980e1a1e1c712c5d9bc8d94c90376b7f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-01soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE sizeYu-Ping Wu
From the output of 'objdump -x dram.elf', the DRAM blob needs 222K memory, but currently only 208K is reserved for it. Since MT8192 has 1MB SRAM L2C, increase SRAM_L2C_END to 0x00300000, and reorganize regions in SRAM_L2C to have larger DRAM_INIT_CODE (256K). The size of OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE is also increased to 252K. BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Asurada booted successfully BRANCH=none Cq-Depend: chrome-internal:3568265 Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-01sb/intel/i82801ix: Factor out common `acpi_fill_madt`Angel Pons
It is the same for all three mainboards. Change-Id: Ic5786bcc29e2549d6fc935d60c699c1cab84b237 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50027 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01sb/intel/common/rcba.h: Guard RCBAx macro parametersAngel Pons
Add brackets around the parameters to avoid operation order problems. Change-Id: I689983b5b937f66b1a520eea61a38fb96c13c007 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50035 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01soc/intel/skylake/Kconfig: Remove duplicated INTEL_DESCRIPTOR_MODE_CAPABLEElyes HAOUAS
Change-Id: I15a1c17e870b04cc1238b54e4f69c227c877ca09 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-01src/soc/intel: Remove CPU_INTEL_COMMON_SMM selectionElyes HAOUAS
CPU_INTEL_COMMON_SMM is already selected in cpu/intel/common/Kconfig file. Also remove duplicated 'CPU_INTEL_COMMON'. Change-Id: I3328da567ac588e9bf6d57481fca117cc302a23a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-01cpu/x86/name/name.c: Clean up includesElyes HAOUAS
Also sort includes alphabetically. Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44315 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01src: Remove unused <cpu/x86/smm.h>Elyes HAOUAS
Change-Id: Ic3f85a8fbc6a84074f45d94514e1dcfa78cb0958 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Change-Id: Ide960d7957e8a95961ec3722ad7478926a84c544 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Also replace 'reg' with 'reg32'. Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49537 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Change-Id: Ib370fc1bae017d084844eece44799676a657323b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h>Elyes HAOUAS
Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45815 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01soc/samsung/exynos{5250,5420}/include/soc/cpu.h: Add missing includeElyes HAOUAS
Use of 'KiB' needs <commonlib/bsd/helpers.h> Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44737 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Also rename 'reg' to 'reg32'. Change-Id: Id741f636162a8a228bca069637993422deb5e09c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Also rename 'reg' to 'reg32'. Change-Id: Ie8dd238a8f10daad9653f44b3ada329c3ede58fe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Also rename 'reg' to 'reg32'. Change-Id: I3aca03dfe20dd0a61cba3ba55146f76e412a2c5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01mb/google/{butterfly,link,rambi,stout}: Remove unused <acpi/acpi_gnvs.h>Elyes HAOUAS
Change-Id: If5c35f3518e2cc4d5760a64e0d38fc4843af498a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50164 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01nb/intel/i945: Drop casts from DEFAULT_{MCH,DMI}BARAngel Pons
They aren't necessary. Removing them changes the binary because the corresponding access macros no longer perform pointer arithmetics. Change-Id: I9723a00b58ee35befdce6a3a51aa2b1fce8efa80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49745 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQSubrata Banik
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip). ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip). Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01security/vboot: Add config for GBB_FLAG_ENABLE_UDCEric Lai
This change adds the missing `GBB_FLAG_ENABLE_UDC` as a config in vboot/Kconfig (just like the other GBB flags) and uses its value to configure GBB_FLAGS Makefile variable. This is done to allow the mainboard to configure GBB flags by selecting appropriate configs in Kconfig. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6b397713d643cf9461294e6928596dc847ace6bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50110 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01bayhub bh720: Add helpers to access PCR registersAngel Pons
The BH720 PCR registers are accessed using an index/data register pair. Introduce some helper functions to clarify the PCR register operations. Change-Id: I1a48b10071af20dca61b7dd90c5a70bc9d1089b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-01sb/intel/i82801gx,ix: Drop MPEN from GNVSKyösti Mälkki
It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01soc/amd: Drop PCNT from GNVSKyösti Mälkki
It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01mb/google/dedede/var/magolor: Configure Acoustic noise mitigation UPDsRen Kuo
Enable Acoustic noise mitigation for magolor and set slew rate to 1/8 which is calibrated value for the board. BUG=b:178678267 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Idea2a801399bb5c7e0b8e59ee7a826c86a44f4ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/50099 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01soc/intel/elkhartlake: Config PlatformDebugConsentFrans Hendriks
UPD PlatformDebugConsent field is not configured. The config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT is available but not used. Use this config value for PlatformDebugConsent. BUG= N/A TEST= Build Intel Elkhart Lake Change-Id: I697fb611dfb23e107fa8ef1543424b9797a7d027 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50108 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01lib/asan.c: Update SPDX licenseFrans Hendriks
lint-000-license-headers reports error. The SPDX identifier contains GPL-2.0 Update the identifier to GPL-2.0-only. BUG = N/A TEST = Build Intel Elkhart Lake Change-Id: If49fd014f14b481163bca6cd3131139b6d95c6d8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01soc/intel/common/sata: Add support for Cannon Lake SATA (HALO)Erik van den Bogaert
Add device ID of Cannon Lake PCH-H Mobile HALO SATA controller in supported device table. Bug=N/A TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully completed Change-Id: Ie1c2aa8273a53c47d7b3571394bcd85b59ab1142 Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-02-01include/device/pci_ids.h: Add Cannon Lake PCH-H SATA dev IDErik van den Bogaert
Add SATA controller ID for Cannon Lake PCH-H Mobile HALO (see document number: 571182) Add SPDX license header Bug=N/A TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully completed Change-Id: Ic7e6ace2a24b4278b04caa58be907d38f4d117cd Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-02-01console/console.h: Move get_console_loglevel() declarationArthur Heymans
If for a stage __CONSOLE_ENABLE__ is 0, then there would be no prototype for a get_console_loglevel() definition. Change-Id: I805078921a5cc1506685f8aada3af5c5241260b7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50083 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01drivers/security/cbnt: Fix bootblock sizeArthur Heymans
Change-Id: Ic5ad9d29f247b6f828501bfacc27a8af08761d55 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-01cpu/x86/mp_init.c: Print out the microcode revision of APsArthur Heymans
It is useful to know if MCU have been applied successfully. On the start of MP init lines similar to: "AP: slot 1 apic_id 1, MCU rev: 0x0700001d" will be printed. The example is taken from the log of an ocp/deltalake. Change-Id: Ia0a6428b41d07f87943f3aa7736b8cb457fdd15a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49840 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01cpu/intel/microcode: Reuse existing function to read MCU revisionArthur Heymans
Change-Id: If198fa68c0a29f46906151e667d7b00e2a3ab00d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01arch/x86/smbios: Add Number Of Power Cords field to be overridenJingleHsuWiwynn
For SMBIOS type 3, add function to override number of power cords Tested=Exectute dmidecode -t 3 to verify. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I7dee3a944a49ffcfdc2f4408d92a17aa39761bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/haswell: Calculate TSEG limit from registersAngel Pons
Done for consistency with other northbridges. Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-01nb/intel/haswell: Create RMRR for iGPUAngel Pons
Taken from Broadwell. Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-01sb/intel/lynxpoint: Use correct port mask for LPT-LPAngel Pons
Lynxpoint LP only has 4 SATA ports. Change-Id: I565a0b2d29ac8fff8b5d87e0f1dbb3667f229365 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47035 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01mb/google/brya: Initiate peripheral busesEric Lai
Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/49007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/volteer: Select SOC_INTEL_CSE_LITE_SKU for volteer baseboardFurquan Shaikh
This change moves the selection of SOC_INTEL_CSE_LITE_SKU into Kconfig under BOARD_GOOGLE_BASEBOARD_VOLTEER instead of requiring each individual board to select it. TEST=Verified that timeless build does not result in any changes. Change-Id: I2d94931fdc3077794bed5cc51708b5a5d9e64972 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/volteer: Drop boldar variantFurquan Shaikh
This variant never really got used and can be deprecated. Change-Id: I5d59460c90266ba5f9c3bdb951f53a37ffae9e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/brya: Change EC -> PCH wake pin to GPP_F17Boris Mittelberg
A new schematic revision indicates that the old wake pin is not used, and brya will only use 1 IRQ pin from EC, routed to GPP_F17 BUG=b:178605367 TEST=Build test Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01Revert "mb/google/hatch/dratini: Describe the privacy_gpio"Ricardo Ribalda
This reverts commit f41645c34d8b22a3d887abd56138ae794fc2dfa5. In Dragonair, during the MP stage, one of the resistors needed for this functionality has been removed. This results in the privacy-switch not readable back by the system. BUG=b:178458332 Change-Id: I0781f338d5ecd89fccee613fb13ea25c59385625 Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocpJohnny Lin
1. These are common OCP/Facebook IPMI OEM commands, move from mainboard into drivers/ipmi/ocp to avoid code duplication and provide better reusability. 2. OCP Tioga Pass enables IPMI_OCP driver. Tested=On OCP Delta Lake and Tioga Pass verify the commands still work correctly. Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-01soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated dsdt.dsl files are same. Change-Id: Ife9bb37817815beec6dad4bc791abba4d91abe00 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-01soc/intel/broadwell/pch/sata.c: Don't enable Bus MasterAngel Pons
Bus Master is not required and reference code does not set it. Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-02-01soc/intel/*: Get rid of custom microcode cachingPatrick Rudolph
Get rid of custom microcode caching in MPinit and SGX code and use the caching introduced in intel_microcode_find() instead. Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01device/oprom/include/x86emu/fpu_regs.h: Fix lint errorFrans Hendriks
`make lint` reports errors and warnings Solve the next errors: - SPACE_BEFORE_TAB - SPACING BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: Ic7062e07a76bf95fe8e2e849f1d14342c9081a23 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49938 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01drivers/intel/fsp2_0: Use CBFS_MCACHE when coreboot tears down CARArthur Heymans
TESTED on ocp/tiogapass. Change-Id: I30560149eeaec62af4c8a982815618be5546531c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01soc/intel/xeon_sp: Use native CAR teardownArthur Heymans
This cleans up the postcar frame setup, which now gets used instead of just going with TempRamExit MTRR's. Note that ramstage CPU init sets up different final MTRRs anyway. TESTED on ocp/deltalake and ocp/tiogapass. Change-Id: I756c2d479fef859a460696300422f08013a300f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01drivers/intel/fsp2_0: Use coreboot postcar with FSP-TArthur Heymans
Allow platforms to use the coreboot postcar code instead of calling into FSP-M TempRamExit API. There are several reasons to do this: - Tearing down CAR is easy. - Allows having control over MTRR's and caching in general. - The MTRR's set up in postcar be it by coreboot or FSP-M are overwritten later on during CPU init so it does not matter. - Avoids having to find a CBFS file before cbmem is up (this causes problems with cbfs_mcache) Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-31soc/intel/*: drop incomplete and unneeded check for DMI SRLOCKMichael Niewöhner
Before enabling IO decode ranges, current code checks if the DMI SRLOCK is set to prevent inconsistencies between LPC PCI cfg registers and LPC DMI registers, when the latter are locked. DMI SRLOCK only applies to PCHs with on-package DMI, but not to PCH-H, PCH-S and others with discrete PCH packages. So this check is at least incomplete. Further, the lock gets applied by FSP and gets reset on a warm reset. Thus, there is no case where the lock would be already set at the places where the DMI registers get written currently. Drop the checks for the reasons mentioned above. Change-Id: I59554ce96bce7f7d1a4ba9b098be9e8466c68eac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49885 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-31soc/amd/common/block/aoac: expand acronym in Kconfig help textFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I08ad12cd7c8de7a7f170d3dc76c8942131687301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50163 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-31util/vboot_lib: Add description.mdKyösti Mälkki
Fixes lint-stable-025 error. Change-Id: I4aa2b2a2ffca69f894a23d7487926016830c9e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50114 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-31mb/emulation/qemu-q35: Use common MADTAngel Pons
Select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT and drop the `acpi_fill_madt` function definition, which is redundant. Tested, still boots to payload. Change-Id: I6ba448f264a478e7ef060ea1dfbf5016a310d528 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-31mb/emulation/qemu-q35: Define and use MMCONF_BUS_NUMBERAngel Pons
Also refactor the machine type checks to avoid code duplication. Tested, still boots to payload with 256, 128 and 64 busses. Change-Id: Ib394ba605bbfeee75aa645e989c23034cceff348 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50025 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-31soc/amd/cezanne/Kconfig: select common PSP gen2 supportFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6068e8b9eb210ce4907fda09208e66e380842de Reviewed-on: https://review.coreboot.org/c/coreboot/+/50152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-31soc/amd/picasso/psp: move soc_get_mbox_address to common PSP gen2 codeFelix Held
The function to get the PSP mailbox address is the same on Picasso and Cezanne, so move it to the common PSP generation 2 code. The function is only used in the same compilation unit, but it can't be marked as static due to the function prototype in amdblocks/psp.h that is still needed for Stoneyridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieea91ef76523d303f948d29ef48e3b2e56293f26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-31soc/amd/stoneyridge/psp: fix check of MSR_PSP_ADDR contentsFelix Held
TEST=Checked documentation, but not verified on hardware. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06399ac9cb9c90701dbcba71cbc808a0d7e6ea0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-31soc/amd/picasso/psp: fix check of MSR_PSP_ADDR contentsFelix Held
If MSR_PSP_ADDR is uninitialized, it's all zeros and not all ones. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iecd3039f63f9d0cb75fe3cb37aee92ba65bbbb50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-31soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDRFelix Held
TEST=Checked that the MSR is the same for Stoneyridge, Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-31soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its registerFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9838e2433004686e3ea82724c55066bcee1f019 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-31soc/amd/cezanne: add soc/cpu.h with CPUID define for Cezanne A0 steppingFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b6d8b0c5ff5e58f6ab487d9fe724534f0108f83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30sb/intel/ibexpeak: Drop invalid ME finalisation functionAngel Pons
Was copied from bd82x6x and none of the PCI IDs matches that of Ibex Peak (PCI_DID_INTEL_IBEXPEAK_HECI1 = 0x3b64). Remove the code. This allows dropping the me_8.x.c dependency, which never made sense. Change-Id: I54df1e080048c0599dbee687ec617fb724cb6634 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-30soc/intel/broadwell/pch: Drop some `config_of` usesAngel Pons
There's no need to die here. Also simplifies merging with Haswell. Change-Id: I3d4bc79b32279180442dbc82126e297f11f1fb80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-30soc/intel/broadwell: Move `ramstage.c` to PCH scopeAngel Pons
The remaining code in this file is PCH-specific. Change-Id: I0e4924e680db9c25aeb222bdd478b3282a77b34f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49946 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel/broadwell: Make `broadwell_init_pre_device` staticAngel Pons
This small function is only used in one place. Change-Id: Ieccdca60fb7837b6406a6b2fd7ebae86958a1afe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49945 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig optionsAngel Pons
Use the existing `MMCONF_BUS_NUMBER` and `MMCONF_LENGTH` symbols. Change-Id: I88dcc0d5845198f668c6604c45fd869617168231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-30device: Drop `mmconf_resource_init` functionAngel Pons
All uses of `mmconf_resource_init` have been replaced in previous patches with `mmconf_resource`, which uses Kconfig symbol values. Change-Id: I4473268016ed511aa5c4930a71977e722e34162a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-30nb/intel/i945: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/gm45: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I635f3615f566502f79bbd81f9f743ce63bba3b1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49758 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/x4x: Define and use MMCONF_BUS_NUMBERAngel Pons
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Moreover, the ASL reservation for MMCONFIG was only for 64 busses. Change-Id: I7366a5096aacd92401535be020358447650b4247 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/pineview: Define and use MMCONF_BUS_NUMBERAngel Pons
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhereAngel Pons
Bootblock enabling needs some special handling. Also, the definition of the `get_pcie_bar` function is incorrect for Ironlake, so remove it. With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work. However, it has not been tested. Using 256 busses should still work. Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: Id88c18129bb773d979ad84bd0bb47188d74d4bc4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49762 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/haswell: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I0d6338f763a78895b1ae14d1ab68253851b6c283 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49763 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel/broadwell: Define and use MMCONF_BUS_NUMBERAngel Pons
Note that ACPI MCFG generation reported too many busses. Change-Id: I5acd26bac675cc818df46f60887f90b76f4580a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50034 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel/broadwell: Use common SMBus codeAngel Pons
Change-Id: I74b21bfde4b76ccb0d432b00c25095f708b1d761 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50030 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30device/Kconfig: Introduce MMCONF_LENGTHAngel Pons
This is necessary because ASL Memory32Fixed values cannot contain operations, even if they can be evaluated to constants. Add a sanity check in pci_mmio_cfg.h to ensure consistency with MMCONF_BUS_NUMBER. Change-Id: I8f0b5edf166580cc12c1363d8d6b6ef0f2854be9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50033 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel/{baytrail,broadwell} Fix building with refcode blobsAngel Pons
Because the refcode blobs are not redistributable, refcode.c is not build-tested. Commit 6271dd8459 (soc/intel/baytrail,broadwell: Use resume_from_stage_cache()) broke building with refcode blobs. Fix a variable redeclaration error by swapping the order of the code, and use consistent names for the variables. Change-Id: Ic8dda8d35086d977b536686e8c80b7961c37860c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-30sb/intel/bd82x6x: Clean up early_thermal.cAngel Pons
Use proper types in readXp functions, define `PCH_THERMAL_DEV`, clean up comments a bit, and use `RCBA32_AND_OR` instead of read32/write32. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I95e054d6e52706e06e313068e61484f6cb9a64e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50038 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/ironlake: Use RCBA macrosAngel Pons
Use defined RCBAx macros over readX/writeX calls. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I87cae75268ef5f329001706e4771e98653d40cd1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50037 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30libpayload/arm*: Add 64bit memory access primitivesPatrick Georgi
Add read64 and write64 for consistency with x86. BUG=b:178785769 Change-Id: I342e3a23201d0b804ea5ecfe47ee3e4bb516de4c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-30mb/amd/majolica: Add an empty bootblock function to handle GPIOZheng Bao
Change-Id: I35da3812a424ea1beef86d043a756a87e6afdaa3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50117 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30util/testing/Makefile.inc: Fix up license headerAngel Pons
Drop unnecessary leading empty lines in comment. Change-Id: Idc0f9d1548336dc2df2d59b18af8d717efa60b68 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-01-30mb/amd/majolica: Add an empty function of mainboard bootblockZheng Bao
Change-Id: I985405b51c81d1e5a3a593bfb759e9850beb2244 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-30drivers/intel/fsp2_0: factor out and improve UPD signature checkFelix Held
In case of a mismatch print both the UPD signature in the FSP and the expected signature and then calls die(), since it shouldn't try calling into the wrong FSP binary for the platform. Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I469836e09db6024ecb448a5261439c66d8e65daf Reviewed-on: https://review.coreboot.org/c/coreboot/+/50090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-30soc/amd,intel: Drop leftover GNVS includesKyösti Mälkki
Change-Id: Ia55d53a9a40846db335aabbe4df8e87f6172f712 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30soc/amd/stoneyridge/southbridge: replace southbridge prefix with fchFelix Held
This aligns the function names with Picasso and Cezanne. Also move the fch_* functions in the header file in the order they get called. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49db8021edae5e537f043bf52eea1be54dc46eca Reviewed-on: https://review.coreboot.org/c/coreboot/+/50124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-30soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP callsFelix Held
Cezanne doesn't have ACPI support yet, but in this case the function always returns 0, so it can already be used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1f5e1f31bf1e52988fcef90daf7b93169e21cbb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50126 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 18:47:02 +0000