diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-31 08:23:00 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 09:00:34 +0000 |
| commit | 487c1a24f59c19539b6039c54176e87864ab91b8 (patch) | |
| tree | cdc1235625d94d0c4d86b56af700dab0c764d412 | |
| parent | 875c21f4912264c25c6277efa405688528ebb50c (diff) | |
nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>
Also replace 'reg' with 'reg32'.
Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49537
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/i945/bootblock.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index f4b46282ca..edb9a8d4d0 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> + #include "i945.h" static uint32_t encode_pciexbar_length(void) @@ -27,6 +28,6 @@ void bootblock_early_northbridge_init(void) * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } |