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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-29 22:33:17 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-31 01:12:18 +0000 |
| commit | 31fdefe5842b7b6f77f341b65cb7851c72fc8516 (patch) | |
| tree | 8df1963ec6f6c5ba23d4e7050bce684c06d7cd32 | |
| parent | 48368892496e333075aa02b7aa2f2d7ba10e8f60 (diff) | |
soc/amd/stoneyridge/psp: fix check of MSR_PSP_ADDR contents
TEST=Checked documentation, but not verified on hardware.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06399ac9cb9c90701dbcba71cbc808a0d7e6ea0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/amd/stoneyridge/psp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index a7fead73dc..69db08dfc3 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -45,7 +45,7 @@ void *soc_get_mbox_address(void) * the MSR instead. */ if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { psp_mmio = rdmsr(MSR_PSP_ADDR).lo; - if (psp_mmio == 0xffffffff) { + if (!psp_mmio) { printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n"); return 0; } |