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Timeless build for QEMU (i440fx/piix4) does not modify the binary.
New patch is add to fix the build in a separate directory from the source.
Change-Id: Ib69437be8ee69ad62fb1dfbbafabc2c4c885b7b2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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BUG=b:283477280
TEST=Able to build and boot google/rex as per Proto 2 schematics
dated 05/16.
+-----------------+------------------------------------+---------------------------+--------+
| GPIO | In Proto 1 | In Proto 2 | Impact |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_C01 | SOC_TCHSCR_RST_L | SOC_TCHSCR_RST_R_L | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_D19 | NC | EC_SOC_REC_SWITCH_ODL | Y |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_E04 | HPS_INT_L | SOC_PEN_DETECT | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_E17 | EN_HPS_PWR | EN_PP3300_SPARE_X | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_F13 | GSPI1_SOC_MISO | GSPI1_SOC_MISO_R | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_F21 | GPIO_F21_SPI_CS_L | SPI_SOC_CS_UWB_L_STRAP | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_H00 | GPIO_H00_SPI_CLK_R | SPI_SOC_CLK_UWB_STRAP_R | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_H01 | GPIO_H01_SPI_MOSI_R | SPI_SOC_DO_UWB_DI_STRAP_R | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_H02 | GPIO_H02_SPI_MISO | SPI_SOC_DI_UWB_DO_STRAP | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_S00 | UNNAMED_8_METEORLAKEU_I137_GPPS00 | SDW_HP_CLK_WLAN_PCM_CLK | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_S01 | UNNAMED_8_METEORLAKEU_I137_GPPS01 | SDW_HP_DATA_WLAN_PCM_SYNC | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_S02 | UNNAMED_8_METEORLAKEU_I137_GPPS02 | DMIC_SOC_CLK0_WLAN_PCM_OUT| N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_S03 | UNNAMED_8_METEORLAKEU_I137_GPPS03 | DMIC_SOC_DATA0_WLAN_PCM_IN| N |
+-----------------+------------------------------------+---------------------------+--------+
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a8c43b0f845d3446188b7c926e482f91e5b45aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75407
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: Ibd7c23a8c7c30ff19e0564d01489fecb3f34dadc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75414
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The IBM SBP1 is an evaluation platform.
It's utilising:
- 4 SPR sockets, having 16 DIMMs each
- 240C/480T at maximum
- 32x CPU PCIe slots
- 2x M.2 PCH PCIe slots
- Dual 200Gbit/s NIC
- SPI TPM
It has an AST2600 BMC for remote management.
It doesn't have:
- External facing USB ports
- Video outputs
- Audio codec
Test:
The board boots to Linux 5.15 with all 480 cores available.
All PCIe devices are working and no errors in ACPI.
All 64 memory DIMMS are working and M.2 devices can be used.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73392
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This commit enables the build for IO Margining, ensuring that ASPM is
disabled and certain FSP knobs are adjusted in coreboot as below
1. Enable DFXEnable
2. Disable PcieGlobalAspm
3. Disable KtiLinkL1En & KtiLinkL0pEn
Since the FSP UPD does not provide all the necessary knobs for IO
Margining, the following settings need to be applied during the FSP
build process:
1. Enable PcdBiosDfxKnobEnabled
2. Disable PchDmiAspm
3. Enable SataTestMode
4. Enable WmphyMargining
5. Disable IioErrorEn
TEST=Build for IBM sbp1 board.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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replace multiple existing EV_* defines with enum ec_enum.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: Id58fc12134915cbeb41cccb54aae9bc3f7dde4b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75324
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The list of outstanding issues on ticket.coreboot.org is formatted as
a Markdown table, which is not supported by Recommonmark. Reformat it
as an embedded reStructuredText table.
Change-Id: Id885e268d55348a365e38c536aed17f974f47840
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75463
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This commit adds support for Intel 800 series chipset. The new chipset
can be uniquely identified by its SPI speed, eSPI speed, and
chipset name.
This commit message is clear and concise, and it accurately describes
the changes that were made to the code. It also includes the following
information:
- Specify the correct chipset name.
"PCH Revision: 800 series Meteor Lake"
- Show the valid eSPI/EC frequency.
"Read eSPI/EC Bus Frequency: 20MHz"
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I70619d9e3ed2bcad86f84a0527e3a0ad13acd706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch adds two new chromeos_*.fmd files for release and debug FSP
builds targeting rex_ec_ish.
`rex_ec_ish` variant would pack ISH firmware into the CSE boot partition
hence, the blob size is expected to increase. Creates separate flash map
layout to ensure ISH work is not impacting on the regular `rex0` project
SPI flash usage.
BUG=b:284254353
TEST=Able to build google/rex_ish_ec board and boot on target hardware.
Change-Id: Ife4663d3ccf80a928646eadaac4c9ab49ad29055
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75471
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates a new variant to support the ISH enablement using
Rex platform.The idea here is to leverage the `rex0` code as much as
possible and add specific support for ISH enablement as per the hardware
schematic differences.
BUG=b:284254353
TEST=Able to build google/rex_ish_ec board and boot on target hardware.
Change-Id: I625fd0b31aed998f4e8f2d139827bc212ee8a90b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75470
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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EFS header is mapped during PSP verstage and bootblock to read some SPI
configuration. After use it is left unmapped. Unmap the EFS region after
use.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim with unsigned PSP verstage.
Change-Id: I865f45a3d25bc639eb8435b54aa80895ec4afd27
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75455
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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cbfs_unmap does not unmap the mapped region from the boot device. This
leads to some resource leaks eg. TLB slots in PSP. Explicitly call
rdev_munmap on the address mapped by cbfs_map.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim with unsigned PSP verstage.
Change-Id: I51b9d066a40103f2ebdf2ef2fc3da13beb467921
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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cbfs_unmap does not unmap the mapped region from the boot device. This
leads to some resource leaks eg. TLB slots in PSP. Explicitly call
rdev_munmap on the address mapped by cbfs_map.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim with unsigned PSP verstage.
Change-Id: If1d355972cc743b8d8c451e1b3f827abd15e98fe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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On FMAP without RW slots, PSP verstage fails to build because of
reference to FMAP_SECTION_FW_MAIN_A_*. Instead extract the offset and
size of relevant sections using fmap_locate_area().
BUG=b:240664755
TEST=Build and boot to OS in Skyrim with unsigned PSP verstage.
Change-Id: I29997534c6843b47a36655431f79e5c70bd17f9b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Only the Intel Quark SoC selected this option and that SoC was dropped
in commit 531023285ea4 ("soc/intel/quark: Drop support"), so drop this
Kconfig option too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic4f1c7530cd8ac7a1945b1493a2d53a7904daa06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75473
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Galileo board was dropped in commit 037c25d4dd8d ("mb/intel/
galileo: Drop support"), so also drop this config file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8c85dc03c3a4a016d6e13f1bee170d1bc6439470
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75472
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Include µcode updates for Broadwell Trad(itional) CPUs.
Tested on Asrock Z97 Extreme6 with an i5-5675C, µcode update loads:
CPU id(40671) ucode:00000022 Intel(R) Core(TM) i5-5675C CPU @ 3.10GHz
Change-Id: I54bb2e767f008b21dcf5d176f8b92a56dcabd129
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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The previous regular expression only matches the line starting with
"Signed-off-by:". If the name and mail address are missing, it can not
find out. The following words should be "name <mail@xxx.com>".
Change-Id: I42cc399e79b65928a6aef87c51e5476c7158d166
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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The SuperIO ACPI name was hard-coded to "SIO0". Allow setting the name
in the device tree so more than one SuperIO can be named.
An upcoming board (purism/librem_l1um_v2) has two SuperIOs - one in the
AST2500 BMC, and a Nuvoton NCT6791D used for hardware monitor, POST
display, etc.
Many boards have references to SIO0 already, so the default name is
still the same for a single SuperIO.
Change-Id: Ibfa6ab7622749e6310ee91530bc3722e8e28d9bb
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75089
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support of variant_devtree_update() function to override
devtree settings for variant boards. Also, add CPU power limit
values for rex baseboard.
BRANCH=None
BUG=b:270664854
TEST=Built and verified power limit values as below log message
for 15W SKU on Rex board.
Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW)
(57000, 57000) PL4 (W) (114)
Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add support to update power limit values for variants.
Until now, each SoC implements this themselves.
To avoid code duplication, add this to common code.
BRANCH=None
BUG=b:270664854
TEST=Built and verified power limit values as below log message
for 15W SKU on Rex board.
Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW)
(57000, 57000) PL4 (W) (114)
Change-Id: I414715f211d816bbfad03a673ca96dd5df94caeb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Restrict memory speed to 6400 MTS as per board design.
BUG=b:282164577
TEST=Verified the settings on google/rex using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3dec383c7c585b80a73089f3403011c5cda61f65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Hook the SaGvFreq, SaGvGear upds so that mainboard can change the
settings via devicetree. Meteor Lake supports 4 SaGv work points and it
can dynamically scale the work point based on memory bandwidth
utilization. Dynamic gearing technology allows the Memory Controller to
run at 1:1, 1:2 or 1:4 ratio of DRAM speed. The gear ratio is the ratio
of DRAM speed to Memory Controller Clock.
BUG=b:282164577
TEST=Verified the settings on google/rex using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I37169880af4019675374594e90735b5d7d0873b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75290
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I384d2f5148cd99ed4282acefaf19885e49d2e79d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Import set_entry_point patch from https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3539414584be0094b0a4fe56dfd64ea79d802edc
to fix issue in binutils 2.40 with LTO when applied to
PE/PE+ binaries (i.e. UEFI).
Change-Id: I3844b53c8761239932ce91c2ff19ed0402321d1a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use verbs enabling jack detect if the EC firmware has been updated
with fixed jack detection.
Test: Build Librem 14 and boot with latest EC, test headset jack
detection.
Change-Id: I57a27b1d51e4f6c7c712bcb2823d21692b9c5ce6
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74364
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Provide system76_ec_cmd() to send arbitrary commands to the EC.
Provide librem_ec_has_jack_detect() to probe for the jack detect fix.
Change-Id: Ic7bda0ce230a3ad68dfeb7b01a0e04f70dab9e5d
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74390
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib8ee07aefdb32b8efe719f484e242b6129596842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add the acpigen_resource_mmio helper function to generate an MMIO range
resource.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I38d55dfcc2892bcb5d253a3aef6ed993cfdba0a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Based on the schematic and vendor ASL code, PCI interrupt lines ABC of
the Ricoh R5C847 PC Card/Media Card/FireWire controller are routed DBC.
From lspci and the schematic this chip is PCI device 1. The original
config copied from the T400 was routed ABCD->BCDA, causing Linux to
issue an "irq 18: nobody cared" message when inserting an SD card.
This is fixed by this patch and the SD card now works properly.
Change-Id: Iede1de72d5369f1aebbac170792733739add3431
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75411
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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"extern" is automatically implied with function declaration.
Change-Id: Ic40218acab5a009621b6882faacfcac800aaf0b9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71890
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Use fw_config to probe lte.
BUG=b:283199751
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I5596f3536b0a21453f89e67615acabbbf6a8409b
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75337
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use fw_config to probe touchpad.
BUG=b:283199751
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ib20abac74683c670c174821b821ede461dbb0163
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Enable touchpad for Google Screebo.
BUG=b:278160238
BRANCH=none
TEST=Build and boot to Google Screebo. Verify touchpad works.
Change-Id: Ib83e5ef5ca497592f5a26aa1e85d793d06d9dd7f
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75412
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The CS42L42 low power audio codec can be connected over SoundWire and
be configured for mainboards to use:
- Data Port 0 and Bulk Register Access
- Data Port 1 is the 64bit data output for the headset
- Data Port 2 is the 64bit data input for the headset
- Data Port 3 is the 64bit data input for the headset
The data port and audio mode properties are filled out as best as
possible with the datasheet as a reference.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
For example this device is connected to master link ID 0 and has strap
settings configuring it for unique ID 0.
chip drivers/soundwire/cs42l42
register "desc" = ""Headset Codec""
device generic 0.0 on end
end
This driver was tested with the rex0 reference design by booting
and disassembling the runtime SSDT to ensure that the devices have the
expected address and properties.
Device (SW00)
{
Name (_ADR, 0x00001001FA424200) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
GpioInt (Edge, ActiveBoth, Exclusive, PullDefault, 0x0000,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0166
}
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0167
}
})
Name (_DSD, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "irq-gpios",
Package () { \_SB.PCI0.HDAS.SNDW.SW00, Zero, Zero, Zero }
},
Package () { "reset-gpios",
Package () { \_SB.PCI0.HDAS.SNDW.SW00, One, Zero, Zero }
},
Package () { "cirrus,ts-inv", One },
Package () { "cirrus,ts-dbnc-rise", 0x05 },
Package () { "cirrus,ts-dbnc-fall", Zero },
Package () { "cirrus,btn-det-init-dbnce", 0x64 },
Package () { "cirrus,btn-det-event-dbnce", 0x0A },
Package () { "cirrus,bias-lvls",
Package () { 0x0F, 0x08, 0x04, One }
},
Package () { "cirrus,hs-bias-ramp-rate", 0x02 },
Package () { "cirrus,hs-bias-sense-disable", One },
Package () { "mipi-sdw-sw-interface-revision", 0x00010000 },
[...]
Package () { "mipi-sdw-source-port-list", 0x02 },
Package () { "mipi-sdw-sink-port-list", 0x0C }
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-bra-mode-0", "BRA0" },
Package () { "mipi-sdw-dp-0-subproperties", "DP0" },
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" },
Package () { "mipi-sdw-dp-1-source-subproperties", "SRC1" },
Package () { "mipi-sdw-dp-2-sink-subproperties", "SNK2" },
Package () { "mipi-sdw-dp-3-sink-subproperties", "SNK3"}
}
})
Name (BRA0, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-bra-mode-bus-frequency-configs",
Package () { 0x00AC4400, ... }
},
Package () { "mipi-sdw-bra-mode-max-data-per-frame", 0x1000 },
Package () { "mipi-sdw-bra-mode-min-us-between-transactions", Zero }
}
})
Name (DP0, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-port-max-wordlength", 0x40 },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-bra-mode-0", "BRA0" }
}
})
Name (MOD0, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-audio-mode-bus-frequency-configs",
Package () { 0x00AC4400, ... }
},
Package () { "mipi-sdw-audio-mode-max-sampling-frequency", 0x0002EE00 },
Package () { "mipi-sdw-audio-mode-min-sampling-frequency", 0x1F40 },
[...]
}
})
Name (SRC1, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-data-port-type", Zero },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
}
})
Name (SNK2, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-data-port-type", Zero },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
}
})
Name (SNK3, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-data-port-type", Zero },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
}
})
}
BUG=b:269497731
TEST=Verified SSDT for SNDW in the OS
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic7cfe2a21c76ba01ad3dea2a5017b28743aeb9f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73279
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The MAX98363 smart speaker amp can be connected over SoundWire and be
configured for mainboards to use:
- Data Port 0 and Bulk Register Access is not supported
- Data Port 1 is the 32bit data input for the speaker path
The data port and audio mode properties are filled out as best as
possible with the datasheet as a reference.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
For example this device is connected to master link ID 2 and has strap
settings configuring it for unique ID 0.
chip drivers/soundwire/max98363
register "desc" = ""Left Speaker Amp""
device generic 2.0 on end
end
This driver was tested with the rex0 reference design by booting
and disassembling the runtime SSDT to ensure that the devices have the
expected address and properties.
Device (SW20)
{
Name (_ADR, 0x000230019F836300) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_DSD, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-sw-interface-revision", 0x00010000 },
[...]
Package () { "mipi-sdw-source-port-list", Zero },
Package () { "mipi-sdw-sink-port-list", 0x02 }
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" },
Package () { "mipi-sdw-dp-1-sink-subproperties", "SNK1" }
}
})
Name (MOD0, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-audio-mode-bus-frequency-configs",
Package () { 0x00927C00, ... }
},
Package () { "mipi-sdw-audio-mode-sampling-frequency-configs",
Package () { 0x3E80, ... }
},
[...]
}
})
Name (SNK1, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-data-port-type", Zero },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
}
})
}
BUG=b:269497731
TEST=Verified SSDT for SNDW in the OS
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie56109d615759e3e5e32782c8782cb2f47014ec4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73278
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Implement PS0 and PS3 methods to support xHCI clock gating in S0ix
suspend and resume.
BUG=b:283989367
TEST=S0iX test passed
Change-Id: Ia5b72b81fd1c0d0b7b90f8d9cbf6ef4aa9da9743
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
The PCI config space access via IO ports uses two 32 bit IO ports.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie99b4f5fc01fb0405243ff108d813ee1a3d35e5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75408
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Changes: https://acpica.org/node/202
Change-Id: I43fc180bd51ff7cb06a67619c8350d28b086bc90
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
BUG=b:276988831
Platform=Rex
Test= inteltool -k
============= Dumping INTEL Key Locker status =============
Key Locker supported : YES
AESKL instructions enabled : YES
===========================================================
Also,
No S0ix issue seen, no impact on power just with this coreboot patch, no stability issue seen.
Boot time delta (using cbmem -t):
Without this CL:
963:returning from FspMultiPhaseSiInit 1,299,043 (98,480)
With this CL:
963:returning from FspMultiPhaseSiInit 1,324,659 (121,995)
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I9919f44623972d7bbae4a9b886e1da4ac7879c98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71120
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Now -mno-mmx is statically set in arch/x86 so remove this option.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I0da7f9f1afb0c8ecae728c45591897ca1d4dfb11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Even though coreboot does not allow floating point operations some
compilers like clang generate code using hw floating point registers,
e.g. SSE %XMMx registers on 64bit code by default. Floating point
operations need to be enabled in hardware for this to work (CR4). Also
in SMM we explicitly need to save and restore floating point registers
for this reason. If we instruct the compiler to not generate code with
FPU ops, this simplifies our code as we can skip that step.
With clang this reduces the binary size a bit. For instance ramstage for
qemu/Q35 drops from 216600 bytes decompressed to 212768.
TEST: See that with x86_64 bit and clang coreboot reaches the payload
without setting the CR4_OSFXSR bit in CR4. Without this change it would
bootloop very early in the bootblock on Qemu Q35.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib8590c55e7aed1ece2aa23b8ea99463396435e11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75316
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Commit f99d6700 ("mb/google/skyrim/var/winterhold: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot winterhold, dump ACPI, verify unchanged
Change-Id: Ia9982fed0fe2093d787ee9506ac5bbadd6cc03f9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75389
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Commit d81ee3f1 ("mb/google/skyrim/var/markarth: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot markarth, dump ACPI, verify unchanged
Change-Id: I5c1cd23c49b512f55e9e13b2164d30dfb7fb682d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75388
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Commit a539893c ("mb/google/skyrim/var/frostflow: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot frostflow, dump ACPI, verify unchanged
Change-Id: I3912fe1b7d3f2a07cb379928cd4f5d87100d3284
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75387
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch adds an enum macro to define the different SaGv work points.
The enum macro is named `sagv_wp_bitmap` and it has three values:
The goal is to choose the optimal SaGv work point for the target
platform after considering the two inputs as power consumption and performance. The first group is for workloads that require high performance, even if it means consuming more power. The second group
is for workloads that can tolerate lower performance, in order to save
power.
SAGV_POINTS_0_1: The highest power consumption, but also the highest
performance.
SAGV_POINTS_0_1_2: A lower power consumption than work point
SAGV_POINTS_0_1, but also a lower performance.
SAGV_POINTS_0_1_2_3: The lowest power consumption, but also the lowest
performance.
Set SaGv work points after reviewing the power and performance impact
with SaGv set to 1 (Enabled) and various considering various work points
between 0-3 being enabled.
BUG=b:267879107
TEST=Able to build google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4af0038f2799a458d1b006270068341f65d36609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75362
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.
On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.
BUG=b:267879107
TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2)
and MRC retraining takes around ~20ms extra compared to SaGv being
disabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds `SaGvWpMask` UPD into the FSP header.
This information is required to set the SaGv work endpoint.
BUG=b:283746904
TEST=Able to build google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If39da58c927cc7b28b46063576f8e246ef9596d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75361
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
A directory for tarballs is needed in any case but it's created at build
time. However, in reproducible build environments the sources are
downloaded before the buildgcc scripts runs and the directory needs to
be created.
Thus, to simplify that, add an empty tarballs directory.
Change-Id: Id3b4bf918c93f10c145f580684e916a4f8bae3b1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
SKU1A C0 has no redriver, so enable SBU muxing in the SoC.
BUG=b:283044004
BRANCH=none
TEST=Voltages are correct on the C0 and C1 AUX bias pins
Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba
Signed-off-by: mike <mike5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Enabling BT for screebo project
BUG=b:278169273
TEST=Check whether BT can connect to Bluetooth device
Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com>
Change-Id: I0ecd62abfbe751e1036948b1490844e7e63d7f0d
Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75352
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This is a PSP FW requirement.
This is only for recovery A/B without ISH header. That means only
Cezanne.
Change-Id: I62616d5a866f66fc71e6c0b31a23c62dc11cf3c6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Hades uses the SODIMM, enable the smbus to see the SPD address for the
memory.
BUG=b:283138024
TEST=i2cdetect -l can see the smubs adapter.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3912a025afaf8388d04a4b08852a84d4a2a6bf06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75399
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Compiler builtins depend on certain CPU features flags to be passed to
the compiler. This may have unwanted side effects as generating code
with FPU registers. Instead use native coreboot code.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4e92d103fa3a6c7a56e813a583b3262676969669
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The payload API of coreboot described in
https://www.coreboot.org/Payload_API does not reflect the current
handoff mechanism to hand the coreboot tables off. Therefore the
arguments supplied by coreboot (cbtable) will currently never be parsed
correctly and libpayload has to search for the coreboot tables by
iterating through memory.
This patch removes the old payload API implementation and just takes the
coreboot table pointer from the first argument on the stack.
Tested: started prodrive/atlas with coreinfo payload
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I51fb0cfc81043cbfe3fc9c8ea0776add2d6a42b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74965
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add CPU PortID for GPIO communities in order to calculate
IOM Aux Bias data correctly.
BUG=b:283044004
TEST=able to detect external display
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: I79f27fb0b6bde0a4ce2466eaf707166a952fad81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Add devicetree and Kconfig entries to enable additional configuration
of the Pericom PI7C9X2G608GP PCIe switch on this board variant.
The amplitude is being adjusted to 425 mV and de-emphasis level to
6.0 mV.
BUG=none
TEST=Read out the PCIe config space values of the switch and check if
they match with the ones configured over SMBus.
Change-Id: I11459f0794278ad614aa6e16c56df1ad578fe2f8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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To improve the rate of data transfer for PCIe root port #2 (00:1c.1) and
root port #3 (00:1c.2) set the max payload size to 256 bytes for both
root ports.
Change-Id: I553f6cf090d799fbbaafb925646c6566d6951a86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75127
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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The data payload size of PCIe root ports can be set to either 128
(default) or 256 bytes. A bigger payload size can improve PCIe data
throughput on the given port. FSP-S provides a parameter to configure
this value.
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Use fw_config to probe touchscreen.
BUG=b:283199751
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I5d8129b3af3aa09e5bc31160de82d9ef7af0dd59
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Override the weak function mainboard_ewl_check() and select OCP_EWL.
Select IPMI_KCS_ROMSTAGE and IPMI_OCP for OCP IPMI commands which are
needed for OCP EWL driver, but they are Meta-specific BMC commands
and don't really work for AC, this change is just for a demonstration
with AC.
Note that FSP UPD promoteWarnings needs to be disabled so that
FSP won't block and can return to coreboot for EWL processing
when memory EWL type 3 error occurs.
Tested=On Intel AC, connected with a faulty DIMM can see
EWL type 3 error being generated and halted with coreboot log:
[DEBUG] Number of EWL entries 3
[ERROR] EWL type: 3 size:32 severity level:1
[ERROR] Major Warning Code = 0x29, Minor Warning Code = 0x04,
[ERROR] Major Checkpoint: 0xb7
[ERROR] Minor Checkpoint: 0x74
[ERROR] Socket 0
[ERROR] Channel 4
[ERROR] Dimm 0
[ERROR] Rank 0
[ERROR] IPMI: ipmi_get_board_config command failed (ret=3 resp=0xc1)
[DEBUG] ipmi send memory training error
[DEBUG] EWL type: 1 size:19 severity level:1
[DEBUG] 0x6392e968: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG] 0x6392e978: 00 00 00
[DEBUG] EWL type: 1 size:19 severity level:1
[DEBUG] 0x6392e97b: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG] 0x6392e98b: 00 00 01
[EMERG] Memory Training Error!
Change-Id: I4602ae356aa6e55ed0611b8ac9a206db127c297c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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If Fastboot is enabled, the next boot will skip MRC and won't be able
to detect MRC error via EWL and still continues booting. Enforce FSP
MRC training in the next boot.
Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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1. Rename set_cmos_mrc_cold_boot_flag() to soc_set_mrc_cold_boot_flag
in case a certain platform may not support this via CMOS data, and
the function could in turn calls mainboard defined method in the
future. Move the code into soc_util.c.
2. Remove redundant static get_system_memory_map() from cpx/romstage.c
and call the soc_util.c one.
Change-Id: Ib7d9bed9092814658f4a0b1d6dcf3c7d79178048
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
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Add PCI IDs to support Raptor Point PCH.
Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2)
Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:
ACPI BIOS error (bug): Could not resolve symbol \
[\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND
BUG=b:283778468
BRANCH=skyrim
TEST=untested, but same error/fix as frostflow variant.
Change-Id: Ic498afcc8b8e0224f344f405e2f1ef6184df1d6b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75340
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
The comment got stale because a few elements from the struct got
dropped.
Change-Id: I83469e24dfab82b9182accb549960dd06d81e02f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
%ebp is used for the stack frame on which the fxrstor address is pushed.
entry64.inc does not trash it so that's fine.
Change-Id: If027437dccac9ad507ceb534c6aae77ea43bdfda
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68896
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:
ACPI BIOS error (bug): Could not resolve symbol \
[\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND
BUG=b:283778468
BRANCH=skyrim
TEST=untested, but same error/fix as frostflow variant.
Change-Id: Ie40541ada508acfa5771ea800249b8a57b168e3b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75339
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:
ACPI BIOS error (bug): Could not resolve symbol \
[\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot frostflow, verify error no longer present in dmesg.
Change-Id: I0b87af6b2c04f9354e6f394a8f987fa660e49134
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75338
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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Generate the RAM ID for Samsung K3KL6L60GM-MGCT.
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 6 (0110)
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I05a2cd5f2235702dea8fd706349ebda6a9ffa2ef
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
This change updates Intel Copyright License for all header files
under Sapphirerapids dir
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP
can be used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
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This is needed to support 9-series PCH-H (e.g. Z97) and Broadwell
non-ULT CPUs (for which more magic is required).
Tested on Asrock Z97 Extreme6: Boots, but ME has to be disabled so that
the system remains on after 30 seconds. Apparently, something Broadwell
MRC.bin does results in the ME being unhappy, as there is no such issue
when not using MRC.bin at all (native RAM init). S3 resume is working.
Change-Id: I7b33660099fa75c5ad46aeeda17b1215729f96c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
BUG=b:282912666
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Iee6a9026a4d210407350bfb7ecc8a058e7ff5c24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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TEST=set the corresponding cbi bit, and saw SPI0 under sysfs
BUG=b:278783755
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I7099cde14cff90ad63e9164769f9913a8284a805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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According to Thermal table 0518, adjust DPTC and STT settings.
BRANCH=none
BUG=b:273636128
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Id1c1884eabc1ea58148270f39eaca836ccc3fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Remove duplicated definitions of ARRAY_SIZE macro across util/ dir.
Instead of duplicates, use the one from commonlib/bsd/helpers.h file.
BUG=b:231765496
TEST=make -C util/cbfstool; make -C util/cbmem;
make -C util/intelmetool; make -C util/superiotool
Change-Id: I29b776586b4f0548d4026b2ac77095791fc9f3a3
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74474
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Grzegorz Bernacki
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The board needs this setting to boot.
Change-Id: I7f507c2478b63daf891430e95b008747b9b95a51
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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Earlier the entire SPI ROM is mapped at the start of verstage and then
unmapped at the end of verstage. With CB:74606, this behavior has
changed. So unmap the hash table CBFS file after usage.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.
Change-Id: I5c605f8ba8bbd571b589b3cdf91e9cc71d711c1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75092
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Currently the SPI ROM is mapped completely when the boot device is
initialized. That mapping remains active throughout the execution time
of PSP verstage. Every 1 MiB of mapped SPI ROM region consumes 1 TLB
Slot in PSP for use during memory mapped or DMA access. With 16 MiB of
mapped SPI ROM + FCH devices + 4 reserved TLB slots, 31 out of 32 total
TLB slots is consumed. This leaves almost no scope for future expansion.
With upcoming programs possibly using 32 MiB SPI ROM, PSP will run out
of TLB slots to support 32 MiB.
Hence instead of mapping the entire SPI ROM upfront, get the SPI ROM SMN
address during the boot device initialization. Update the boot device
region operations to map and unmap the SPI flash with the desired offset
and size using the SVC call. Then anytime a memory mapped SPI ROM access
is performed: map the required area, read the data and immediately unmap
the area. There is no update required when using CCP DMA, since the
concerned SVC call performs mapping and unmapping of the required SPI
flash area implicitly.
With these changes, maximum of 8 slots(size of RO section) might get
used at any point in time during the PSP verstage execution.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.
Change-Id: Icd44ea7b2a366e9269debcab4186d1fc71651db2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74606
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add sending Meta's BMC SEL for memory training error occurred in EWL
type 3 error.
The detail definition of EWL (Enhanced Warning Log) can be found in the
specification document -- BIOS Data ACPI Table (BDAT) Interface
Specification v4.0 Draft 5:
https://uefi.org/sites/default/files/resources/BDAT%20Specification%20v4.0%20Draft5_0.pdf
Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69147
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The Gazelle 18 (gaze18) is a Raptor Lake-H board.
Tested with a custom TianoCore UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots
- M.2 NVMe SSD slot
- M.2 SATA SSD slot
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.6
Not working:
- Discrete/Hybrid graphics
Change-Id: I4599bf12c0f3048f9328f336cc8971400f5fd1a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
|
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Currently unsigned PSP verstage binary is copied from ELF file only when
required in amdfw*.rom. If a signed PSP verstage binary is supplied
while building amdfw*.rom, then it is dropped. Copy the unsigned PSP
verstage binary always so that it can be used for signing directly from
the CI build infrastructure instead of a locally built binary.
BUG=None
TEST=Build Skyrim BIOS image and ensure that the unsigned PSP verstage
is part of the build artifacts.
Change-Id: If797dcfd20aa2991f3517904ef862406b9b9875c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75334
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Pujjoteen5 support WWAN 5G device, use variant.c to handle the
power on sequence.
BUG=b:279835626
TEST=Build and check WWAN 5G power on sequence.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I7dc72f2c705bcb41745f4bf08bef286773fe8b13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75327
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Measured the I2C frequency meets spec
1. I2C0 (TPM): 976.1 Khz
2. I2C1 (TouchScreen); 394.0 Khz
3. I2C2 (WCAM); 377.9 Khz
4. I2C3 (Audio): 390.0 Khz
5. I2C5 (Touchpad): 389.3 Khz
BUG=b:283374537
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
and check all I2C devices measurement result
Change-Id: If6e3a4a2b1ac642561015a290e6579238c3c2b1b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Set the DmaProperty in the device's _DSD so that the OS can treat the
device as untrusted.
BUG=b:278310256
TEST=cat /sys/bus/pci/devices/<wifi>/untrusted == 1
iperf3 -c <iperf3-server> -t 60 (No performance regressions seen)
Change-Id: I06369a19afa5b881b26f5c1eb243e2db41a9bb36
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75095
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
|
|
Show an error if an option table is used, and the ramtop entry is not
defined on a platform that uses it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie48f0766b29be8e1fb0c1f71c4b2ce6ed20e6207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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CB:37152 was supposed to be uprev to Linux's kconfig, but it got this
one case wrong, Linux never returned "0" [1]. As a result, when an
option has default value different than 0, and it was changed to 0,
savedefconfig skips saving it. However, during the build from such
defconfig the option is assigned default value.
TEST=Set SEABIOS_DEBUG_LEVEL to 0 and see that savedefconfig writes
it to defconfig file.
[1] https://github.com/torvalds/linux/commit/7cf3d73b4360e91b14326632ab1aeda4cb26308d
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I821e45dcec99904fab85f136298cbd0315237ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72650
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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During the cleanup of copyright lines, this file was incorrectly changed
to remove the copyright line. It is not originally a part of the
coreboot project, having been pulled in and adapted for use in coreboot.
As such, and with the ISC license specifying that the copyright line
should be maintained, the copyright line has been restored.
See coreboot ticket # 479 for more information.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia234cebd0a6d49d03e40c5a57cd346a07f3e4b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Set all GPIOs to their target functions and do not depend on FSP to
configure them. The board support has stabilized and was tested with
many PCIe devices. There is no need to detect CLKREQ signals so we may
hardcode them.
TEST=Boot MSI PRO Z690-A DDR4 to Linux and check if all ASPM and Clock
PM features' state on PCIe root ports are the same before and after
the change.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I01dc83ce23ca27525b8905665da942510f249824
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Disable backlight before turning on bridge, otherwise the bridge will
initialize failed.
Fixes: d5c1e1(mb/google/corsola: Add support for MIPI panel)
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I7d10bf9e8675b2fb03bfd1e294af66207b9b0620
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75354
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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BUG=b:278156430
TEST=verify the fingerprint on screebo
Change-Id: I986e470b28145f7b17427e794055929a4283c721
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75287
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The upstream kernel privacy screen driver uses HID GOOG0010 to look for
firmware node to use. This method is used on other boards, e.g. redrix.
See: drivers/platform/chrome/chromeos_privacy_screen.c in linux sources.
Update jinlon gfx ACPI node to work with that.
BUG=b:279092050
TEST=privacy protection screen works with 5.15 and 4.19 kernels
Change-Id: Icba41e7f2be7292f713fea10dbe69b3ca128bde7
Signed-off-by: Kornel Dulęba <korneld@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75289
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Disable unused gpio for LTE daughter board, WFC and stylus.
BUG=b:277148122
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I6cc61321cd96a10dd34ff6cd9fcabe85a64bbfa9
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75293
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The support for the board has stabilized and PCIe ports have been
tested with many devices. Although hotplug is not commonly used
and it seems pointless to keep it enabled, so disable it.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I338c55cb57d971badd08235b71626a710fafb829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The Bochs graphics adapter remaps the legacy VGA ioports
(0x3c0 -> 0x3df) to its MMIO region at offsets 0400 - 041f.
Currently bochs_vga_write() calculates a wrong offset when
accessing these ioports, which causes the boot splash image
not displayed when using the legacy-free pci variant of the
Bochs graphics adapter.
TEST=Build coreboot for QEMU x86 i440fx with a boot splash image
included, boot coreboot.rom with QEMU with '-device secondary-vga'
and verify the boot splash image is correctly displayed.
Fixes: efaf1b32ba1e ("drivers/emulation/qemu/bochs: Rewrite driver")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Change-Id: I4acc71e3d6ef5161ab62e6714c94b7643c4c0972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75146
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The named choice isn't needed here, so get rid of it. This fixes the
build notice:
build/auto.conf:notice: override:reassigning to symbol LAPIC_ACCESS_MODE
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I70628007319a0ee2830dc4c9cb3b635d8190264b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75133
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Select INTEL_GMA_HAVE_VBT so VBT files are added by default. This board
has two specific VBT files that are hard-coded in the Makefile. Hence
set an empty INTEL_GMA_VBT_FILE string.
Change-Id: I0508c8016da06b401d6fbefd6e5cec1af018a5c8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Reformat the string, fix whitespace, add single-quote before
genitive `s`, and correct the GPU tool name `intel_reg`.
Change-Id: I277603063806927837867a454ae0875578228109
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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