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authorBora Guvendik <bora.guvendik@intel.com>2023-05-15 14:35:22 -0700
committerFelix Held <felix-coreboot@felixheld.de>2023-05-26 17:59:15 +0000
commite9efd3248550e01a5043860f25239a799d5b19bc (patch)
tree1849af0f2edfeb00685ca1ce91eebb238d2b5a40
parent9f15dee56d7fbebe22cb15d55279f05c85a75832 (diff)
mb/google/rex: Set frequency and gears for SaGv points
Restrict memory speed to 6400 MTS as per board design. BUG=b:282164577 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3dec383c7c585b80a73089f3403011c5cda61f65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
-rw-r--r--src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 09d49d05a9..bd5b0bb237 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -41,6 +41,18 @@ chip soc/intel/meteorlake
register "sagv" = "SAGV_ENABLED"
+ register "sagv_freq_mhz[0]" = "2133"
+ register "sagv_gear[0]" = "4"
+
+ register "sagv_freq_mhz[1]" = "6000"
+ register "sagv_gear[1]" = "4"
+
+ register "sagv_freq_mhz[2]" = "6400"
+ register "sagv_gear[2]" = "4"
+
+ register "sagv_freq_mhz[3]" = "5600"
+ register "sagv_gear[3]" = "2"
+
# Set on-board graphics as primary display
register "skip_ext_gfx_scan" = "1"