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2023-06-04lib: Support localized text of memory_training_desc in ux_locales.cHsuan Ting Chen
To support the localized text, we need to get the locale id by vboot APIs and read raw string content file: preram_locales located at either RO or RW. The preram_locales file follows the format: [string_name_1] [\x00] [locale_id_1] [\x00] [localized_string_1] [\x00] [locale_id_2] [\x00] [localized_string_2] ... [string_name_2] [\x00] ... This code will search for the correct localized string that its string name is `memory_training_desc` and its locale ID matches the ID vb2api returns. If no valid string found, we will try to display in English (locale ID 0). BUG=b:264666392 BRANCH=brya TEST=emerge-brya coreboot chromeos-bmpblk chromeos-bootimage Change-Id: I7e3c8d103c938a11b397c32c9228e44e31c3f01d Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-04mb/google/myst: Add PCIe shutdown workaroundJon Murphy
On Myst, the FSP is shutting down the PCIe lanes that the SSD is on. Enable hotplug to force the FSP to keep the lanes active. BUG=b:284213391 TEST=Boot to OS Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe Reviewed-on: https://review.coreboot.org/c/coreboot/+/75583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-06-04mb/google/myst: Enable S0ixJon Murphy
Enable s0ix on Myst. BUG=b:277215113 TEST=builds Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74279 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04libpayload/uhci: Return expected length for control/bulk transfersNico Huber
Libpayload's USB API was changed in commit e9738dbe2b (libpayload: Make USB transfer functions return amount of bytes). However, the UHCI driver was never adapted. Instead of returning 0 for success, we can return the expected data length as a best effort. We won't be able to catch short transfers this way, but previously working cases will work again. Change-Id: I31d7de495a46af401e2cbe5a3b8f6349facad8ff Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-04vc/intel/fsp2: Drop Intel Quark FSP headersFelix Singer
Intel Quark was dropped in commit 531023285e. Thus, drop the remaining FSP headers. Change-Id: Ie3c11c6f68d879b944f7b4ed0fde0ee4aae204b9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-04crossgcc: Upgrade LLVM from version 16.0.4 to 16.0.5Elyes Haouas
Change-Id: I1f227bf55bac51e6226ca5d13156e54220e33629 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75635 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04crossgcc: Upgrade CMake from version 3.26.3 to 3.26.4Elyes Haouas
Change-Id: Id6dca6be8f7a82eadcbc18b4736219faf51b843c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-04soc/intel/meteorlake: Apply PCIe RP mask based on SoC typeSubrata Banik
This patch ensures to update the FSP-M UPDs related to PCIe RP mask properly as per the SoC type. For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P whereelse PCIe RPs are from PCH die in case of MTL-S. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: Ice81553274682476bb4c927061b1196dc142836d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75608 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-04mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_PSubrata Banik
Intel/MTLRVP is built with Intel Meteor Lake-U SoC, so select it. Currently, there is no functional difference, but in the future FSP UPD parameters can be overridden properly. BUG=b:276697173 TEST=Able to build and boot intel/mtlrvp. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8b1dec47ef9d12ac50317b86c4f0bc5fbe4e4dc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75607 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04mb/google/rex: Select SOC_INTEL_METEORLAKE_U_PSubrata Banik
Google/Rex is built with Intel Meteor Lake-U SoC, so select it. Currently, there is no functional difference, but in the future FSP UPD parameters can be overridden properly. BUG=b:276697173 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4c233e0a8ce58998dc1a0379662e386f9b3d0073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75612 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-04soc/intel/meteorlake: Introduce different SoC flavors of Meteor LakeSubrata Banik
This patch introduces the different SoC flavors of Intel Meteor Lake as: * MTL-U * MTL-P * MTL-S MTL-U and MTL-P are PCH less designs, while MTL-S is with PCH die. The task for mainboard is to specify the correct SoC type rather than selecting the MTL SoC by default. This change is necessary to support the different SoC flavors of Intel Meteor Lake. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04soc/intel/meteorlake: Hook up UPD PchHdaSdiEnableRonak Kanabar
Hook the PchHdaSdiEnable UPD so that mainboard can change the settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes. BUG=b:273962021 TEST=Verified the settings on google/rex using debug FSP logs. Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75529 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3194_81, previous version being 3165_81. FSPM: 1. Add 'PchPcieRpEnableMask' UPD 2. Address offset changes Add "FspProducerDataHeader.h" file to support MRC version Info BUG=b:284803304 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75519 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-03Docs: Update sphinx targets with the build directoryMartin Roth
Because Makefile.sphinx looks like a standard makefile from the sphinx project, it probably shouldn't be updated without good reason. This change lets us update the output directory and tell the Makefile.sphinx where we want the output. Also fix the spacing on PDFLATEX to match the new SPHINXDIR variable. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iab111e8feea8ec02260f39636e7c17fd1cae7c30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-03Docs: Add a test target for the documentationMartin Roth
The test target will run, but won't fail the build if there are issues. This is so it can be added to the jenkins build and run until it passes. At that point, it can be made to fail if there's an error. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5810643ee143f9db4f1cd388531161d4398d596c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-03mb/google/rex: Create karis variantTyler Wang
Create the karis variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:285195072 TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_KARIS Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-03mb/google/brya/var/anahera: Generate RAM ID for K4UCE3Q4AB-MGCLWisley Chen
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281950933 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I75818b8a34d010fc0efe90c7625162e40e3b0dca Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-03mb/google/brya/var/redrix: Generate RAM ID for K4UCE3Q4AB-MGCLWisley Chen
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281943392 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I79b29b1195468272c7f64a0eeb15d032eff8c1d3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-03spd/lp4x: Generate initial SPD for K4UCE3Q4AB-MGCLWisley Chen
Generate initial SPD for Samsung K4UCE3Q4AB-MGCL BUG=b:281943392 BRANCH=firmware-brya-14505.B TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: I0a860f3f9c307e70f63a53435cc26e6f278d0a17 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-06-03mb/starlabs/starbook: Fix the ramtop CMOS entrySean Rhodes
The ramtop entry has to be 10 bytes long, and it was incorrectly set to 10 bits, instead of 10 bytes. Change this to 80. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I506f9d98a389dd859038fd270c5e344b65f514f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75420 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-03lib/dimm_info_util.c: Add newlines to log messagesFred Reitberger
Add newlines to log messages to prevent them from running into each other. Change-Id: I4f61c80385f384a3734a5122ccb4161c1ed7c6c5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75589 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02Docs: Add help target and .phony identifiersMartin Roth
This change adds a help target so we can see what the valid targets are and what they do, and also identifies the phony targets. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie61d44d87e8628e12d01f3355360e2a679b5ce85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02payloads/edk2: Set max variable size to 0x8000 for SMMSTORESean Rhodes
SMMSTORE requires 0x8000, compared to the default value of 0x10000. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I10d2a5a0c1d729d83e0b62bb9430863317b883cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-06-02util/amdfwtool: Add ability to split hash tableKarthikeyan Ramasubramanian
Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-02Docs: Add sphinx to the documentation's "all" targetMartin Roth
The all target really should build the expected output. At this point, that means sphinx as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ibbceddd013605f5f7e11707480ae2a1e5d012a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02util/docker: Split coreboot-sdk test into its own docker imageMartin Roth
This allows the coreboot-sdk docker image to build properly even if the testing fails, and keeps the added overhead out of the coreboot-sdk image. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6488799256f57ad64e14c93e7317b7ad2a71781c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02soc/amd/common/block/graphics: Add missing pci_rom_free()Grzegorz Bernacki
pci_rom_probe() can allocate memory when mapping a CBFS file, so pci_rom_free() should be called before leaving the function. BUG=b:278264488 TEST=Build and run with additional debug prints added to confirm that data are correctly unmapped Change-Id: Ie6fbbfd36f0974551befef4d08423a8148e151e7 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74779 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-06-02device/pci_rom: Add simple pci_rom_free()Grzegorz Bernacki
It adds simple function, which frees the memory which could be allocated by pci_rom_probe(). In the next step it will be modified to free only memory, which was mapped from CBFS. BUG=b:278264488 TEST=Build and run with additional debug prints added to confirm that data are correctly unmapped Change-Id: Ibc9aad34b6bf101a3a0c06b92ed2dc6f2d7b9b33 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74778 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02soc/amd/common/block/cpu: Refactor ucode allocationGrzegorz Bernacki
Move microcode load/unload to pre_mp_init and post_mp_init callbacks. It allows to make sure that ucode is freed only if all APs updated microcode. BUG=b:278264488 TEST=Build and run with additional debug prints added to confirm that data are correctly unmapped Change-Id: I200d24df6157cc6d06bade34809faefea9f0090a Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-06-02amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenixFred Reitberger
BUG=285390041 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74971 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEXFred Reitberger
The phoenix SoC does not support multiple EFS locations. Set the default to the only valid value and prevent mainboard overrides by making the option non-user-configurable. TEST=build birman-phoenix Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I0f720dbadf2d28a3c39daa4bd653a407be4893d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-02soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-02soc/amd/mendocino: Add manifest generation to MakefileGrzegorz Bernacki
This adds manifest generated by amdfwtool to CBFS. BUG=b:224780134 TEST=Tested on Skyrim device Change-Id: I13c9d322735e0979484b120c665fb100cf187eab Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74267 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-06-02amdfwtool: Add --output-manifest optionGrzegorz Bernacki
Passing this option tells amdfwtool to create a text file, containing the versions of the blobs below: - PSP bootloader (type 0x01), - SMU firmware (type 0x08), - AGESA bootloader 0 (type 0x30), - PSP bootloader AB (type 0x73). Created file can be embedded into CBFS which allows to read the version of blobs at runtime. This way version of blobs used to build the coreboot image can be verified at runtime and also from the binary file. Format of manifest file is following: $ cat build/amdfw_manifest type: 0x01 ver:00.35.00.13 type: 0x08 ver:00.5a.23.a6 type: 0x30 ver:2a.14.b0.10 type: 0x73 ver:00.35.00.13 BUG=b:224780134 TEST=Tested on Skyrim device Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-02mb/google/rex/variants/screebo: add FW_CONFIG for audio/DBSimon Zhou
This patch adds FW_CONFIG to accommodate different Screebo BOM components across various SKUs. 1. DB_CONFIG for DB_TPEC/DB_TBT/DB_UNKOWN 2. AUDIO for ALC1019_ALC5682I_I2S/AUDIO_UNKNOWN BUG=b:278169268 TEST=build pass Change-Id: I928aae61d4936509a7b68f4041c0cd72f298e83d Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-02include/cpu/x86: Simplify en/dis cache functionsHimanshu Sahdev
Implementation of enable/disable cache functions aren't complex, simply drop cr0 variable usage, still maintains good readablity. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: I81688e8bbb073e1d09ecf63f3f33e1651dbd778e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75552 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-01soc/intel/jasperlake: Enable early caching of RAMTOP regionSean Rhodes
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-01mb/google/myst: Add ELAN touch screenEric Lai
Follow the eKTH7B18U_Product_Spec_V1.1 to add the device. BUG=b:284381267 TEST=Check touch screen can detect in coreboot. [INFO ] \_SB.I2C1.H010: ELAN Touchscreen at I2C: 02:10 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I4bd521410953892a477020a872de0d882001b178 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-06-01mb/google/myst: Add ELAN touch padEric Lai
Follow the data sheet SA577C-12C0, Rev. 1.1 to add the device. BUG=b:284381266 TEST=check touch pad can detect in coreboot. [INFO ] \_SB.I2C0.D015: ELAN Touchpad at I2C: 01:15 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0eb0ee1e6cb9c15bfe3964af6ce2ed02eee370a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-06-01mb/google/myst: Add codec RTL5682 and amp RTL1019Eric Lai
Follow the schematic_0502 to add the audio codec and amp. BUG=b:270109435 TEST=Check device can detect in coreboot. [INFO ] \_SB.I2C3.RT58: Realtek RT5682 at I2C: 04:1a [INFO ] \_SB.I2C3.D029: Realtek SPK AMP R at I2C: 04:29 [INFO ] \_SB.I2C3.D02A: Realtek SPK AMP L at I2C: 04:2a Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Icfec8d99be8fde986c5516e0c4cd50dae1edfa98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75477 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Use SSD type for SATA portsMario Scheithauer
There are only SSD connected to SATA ports on this mainboard. To prevent misbehavior, set the correct hard drive type for enabled SATA ports. BUG=none TEST=Boot into OS and check the stability of the SSD Change-Id: I2c2b0548865e87859a1d742295e09a731bfb3f76 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-01soc/intel/apollolake: Make hard drive type for SATA ports configurableMario Scheithauer
Intel's APL FSP offers the possibility to select the connected hard drive type to SATA ports. One has the option to choose between HDD ('0' - default) and SSD ('1'). This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I52c3566fb3c959ada6be33f0546ac331f4867d10 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-01mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2Mario Scheithauer
Due to mainboard restrictions a SATA link at Gen 3 can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01soc/intel/apollolake: Make SATA speed limit configurableMario Scheithauer
In cases where there are limitations on the mainboard it can be necessary to limit the used SATA speed even though both, the SATA controller and disk drive support a higher speed rate. The FSP parameter 'SpeedLimit' allows to set the speed limit. It should be noted that Gen 3 equals the default value '0'. This means that inside FSP the same code is executed. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75364 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01soc/intel/common/crashlog: Check cbmem pointer before copying recordsPratikkumar Prajapati
Check existence of crashlog records in CBMEM before copying them to BERT, otherwise it can lead to NULL pointer access. Bug=None TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog. Change-Id: I4288011866283a3a5fb8ec9e10cd51b794052b4e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75528 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01soc/intel/common/crashlog: Check for invalid recordPratikkumar Prajapati
Do not copy the crashlog record if the record is 0xdeadbeef Bug=None TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog. Change-Id: I0edbf6902685a882876d525e63c5b602c1590ea1 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-01soc/intel/common/crashlog: Fix checking PMC record sizePratikkumar Prajapati
Check pmc_record_size variable for collecting PMC records, instead of cpu_record_size variable. Bug=None TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog. Change-Id: I4c35ba2bcf757231aa2872802eb82d4d50742cd9 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75526 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01mb/google/guybrush: Move helper AOAC for console to AOAC headerKonrad Adamczyk
BUG=b:217968734 TEST=Build guybrush firmware Change-Id: I93dfa50cd1116e0f6652186acb37fd43d638cf84 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75491 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01drivers/ocp/vpd: Overwrite Linux payload's kernel command via VPDJohnny Lin
Add a new Kconfig LINUXPAYLOAD_CMDLINE_VPD_OVERWRITE that can overwrite Linux payload's kernel command line from VPD. Currently only overwrite Linux kernel command line 'loglevel' via VPD key 'kernel_log_level'. TESTED=On OCP Delta Lake, with kernel_log_level set to 0, warm reboot time can see about 10 seconds improvement comparing to kernel log level 7. Change-Id: Idf06c7ab9958c940fc3b23d560bb9dade991a6da Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-06-01device/pci: Limit default domain memory windowNico Huber
When the default pci_domain_read_resources() is used, keep 32-bit memory resources below the limit given by CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT. This serves as a workaround for missing/wrong reservations of chipset resources. This will help to get more stable results from our own allocator, but is far from a complete solution. Indvi- dual platform ASL code also needs to be considered, so the OS won't assign conflicting resources. Most platforms have reserved space between 0xfe000000 and the 4G barrier. So use that as a global default. In case of `soc/intel/common/`, use 0xe0000000 because this is what is advertised in ACPI and there are traces of resources below 0xfe000000 that are unknown to core- boot's C code (PCH_PRESERVED_BASE?). Tested on QEMU/Q35 and Siemens/Chili w/ and w/o top- down allocation. Fixes EHCI w/ top-down in QEMU. Change-Id: Iae0d888eebd0ec11a9d6f12975ae24dc32a80d8c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01mb/google/corsola: Fix MIPI panel power on/off sequenceRuihai Zhou
Based on the power sequence of the panel [1] and PMIC datasheet [2], the power on T2 sequence VSP to VSN should be large than 1ms, but it's -159us now, and the power off T2 sequence VSP to VSN should be large than 0ms, but it's less than 0 now. Let's modify the power sequence to meet the datasheet requirement. [1] HX83102-J02_Datasheet_v03.pdf [2] TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:282902297 TEST=power sequence T2 pass Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Ib1625c6a211f849071393f69eaf5c649a8e7f72e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75298 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01soc/mediatek/common: Add support for power supply TPS65132SRuihai Zhou
The TPS65132S is designed to supply positive/negative driven application. It communicates through standard I2C compatible interface, and it intergrates a EEPROM whose contents will be loaded into the register at startup. Since TPS65132S is used in staryu and geralt projects, we move the implementation to mediatek/common. The datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:282902297 TEST=boot starmie to firmware screen Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Iad2c9bdea5824455efcef18b44876111061cfa1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75488 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01mb/google/nissa/var/uldren: Add DPTF parametersDtrain Hsu
The DPTF parameters were verified by the thermal team. BUG=b:282598257 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1f38ef52d3906960f8b692595fcc3b39bc000243 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-06-01device/resource_allocator_v4.c: Fix printing unsigned integersArthur Heymans
Use the proper format specifier for unsigned integers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5e39377d62981229531027b3153d5b343a0a7538 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75400 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01device/allocator: Allow for multiple domain resources of a typeArthur Heymans
Don't assume only one IO and one MEM domain resource. Currently the code is awkward for bridge devices where loops over resources are done twice. This would be avoided on top of other patches that improve the allocator (topic:allocator) by adding a top-down mode. However those patches break the tree and having the option to have multiple resources per type would make it easier to get those patches in without breaking the tree. Change-Id: I3d3a60c9a4438accdb06444e2b50cc9b0b2eb009 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67018 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-06-01include/cpu/x86: Skip `wbinvd` on CPUs with cache self-snooping (SS)Subrata Banik
This patch refers and backport some of previous work from Linux Kernel (https://lore.kernel.org/all/1561689337-19390-3-git-send-email-ricardo. neri-calderon@linux.intel.com/T/#u) that optimizes the MTRR register programming in multi-processor systems by relying on the CPUID (self-snoop feature supported). Refer to the details below: Programming MTRR registers in multi-processor systems is a rather lengthy process as it involves flushing caches. As a result, the process may take a considerable amount of time. Furthermore, all processors must program these registers serially. `wbinvd` instruction is used to invalidate the cache line to ensure that all modified data is written back to memory. All logical processors are stopped from executing until after the write-back and invalidate operation is completed. The amount of time or cycles for WBINVD to complete will vary due to the size of different cache hierarchies and other factors. As a consequence, the use of the WBINVD instruction can have an impact on response time. As per measurements, around 98% of the time needed by the procedure to program MTRRs in multi-processor systems is spent flushing caches with wbinvd(). As per the Section 11.11.8 of the Intel 64 and IA 32 Architectures Software Developer's Manual, it is not necessary to flush caches if the CPU supports cache self-snooping (ss). "Flush all caches using the WBINVD instructions. Note on a processor that supports self-snooping, CPUID feature flag bit 27, this step is unnecessary." Thus, skipping the cache flushes can reduce by several tens of milliseconds the time needed to complete the programming of the MTRR registers: Platform Before After 12-core (14 Threads) MeteorLake 35ms 1ms BUG=b:260455826 TEST=Able to build and boot google/rex. Change-Id: I83cac2b1e1707bbb1bc1bba82cf3073984e9768f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-01cpu/x86/cache: Call wbinvd only once CR0.CD is setJeremy Compostella
This patch removes the wbinvd call preceding CR0.CD setting in disable_cache() to improve the boot time performances. According to some experimental measurements, the wbinvd execution takes between 1.6 up and 6 milliseconds to complete so it is preferable to call it only when necessary. According to Intel Software Developer Manual Vol 3.A - 12.5.3 Preventing Caching section there is no need to flush and invalidate the cache before settings CR0.CD. The documented sequence consists in setting CR0.CD and then call wbinvd. We also could not find any extra requirements in the AMD64 Architecture Programmer’s Manual - Volume 2 - Memory System chapter. This extra wbinvd in coreboot disable_cache() function does not seem documented and looking into the history of the project got us all the way back to original commit 8ca8d7665d67 ("- Initial checkin of the freebios2 tree") from April 2003. Even the original disable_cache() implementation (see below) is a bit curious as the comment list two actions: 1. Disable cache cover by line 74, 75 and 77 2. Write back the cache and flush TLB - Line 78 But it does not provide any explanation for the wbinvd call line 76. 68 static inline void disable_cache(void) 69 { 70 unsigned int tmp; 71 /* Disable cache */ 72 /* Write back the cache and flush TLB */ 73 asm volatile ( 74 "movl %%cr0, %0\n\t" 75 "orl $0x40000000, %0\n\t" 76 "wbinvd\n\t" 77 "movl %0, %%cr0\n\t" 78 "wbinvd\n\t" 79 :"=r" (tmp) 80 ::"memory"); 81 } BUG=b/260455826 TEST=Successful boot on Skolas and Rex board Change-Id: I08c6486dc93c4d70cadc22a760d1b7e536e85bfa Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-05-31mb/google/rex/var/screebo: Add MIPI camera devicejason.z.chen
Enabling MIPI UCAM for screebo project BUG=b:277883010 TEST=none Signed-off-by: jason.z.chen <jason.z.chen@intel.corp-partner.google.com> Change-Id: Id06e5c162d911a4bd78190757c25e7f760160a8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-31device/dram: Update RDIMM classification from RIMM to DIMMZiang Wang
Registered DIMM should be 'FORMFACTOR_DIMM' with 'DETAIL_REGISTERED' instead of 'FORMFACTOR_RIMM', RIMM has been EOL for so many years. Memory form factor info is now correct on 4th Gen Xeon server platform with registered DIMM. Signed-off-by: Ziang Wang <ziang.wang@intel.com> Signed-off-by: Kehong Chen <kehong.chen@intel.com> Change-Id: I1eea4717a2d60c6100c262a2284a2ac5109f114a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-31mb/google/rex/var/screebo: Set TCC to 90°CWentao Qin
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit (TCC) activation feature for proto phase. BUG=b:282865187 BRANCH=None TEST=Build FW and test on Screebo board Change-Id: I3a929aa20a700376d2a0a150911fed34e67f78eb Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75360 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/dedede/var/boxy: Fix filename "MakeFile.inc" to "Makefile.inc"Kevin Yang
Incorrect filename "MakeFile.inc" cause gpio.c can not be complied. Rename to "Makefile.inc" and confirm gpio.c can load correctly. BUG=b:281620454 BRANCH=dedede TEST=build and confirm gpio.c can be loaded Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I39947c66de04695e5242ab1affc328894f34f9f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75520 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/rex: Move I2S config from common to boardKapil Porwal
Move I2S config from common to board. BUG=none TEST=Build google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I51ca902e9b0077d5d5cc9c3507d26301a0f61bc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75513 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/rex: Enable SoundWire codecsKapil Porwal
Enable drivers for SoundWire codecs and define the topology in the devicetree for the rex0 variant with the SoundWire daughter board connected. +------------------+ +--------------------+ | | | Headphone Codec | | Intel Meteor Lake| +--->|Cirrus Logic CS42L42| | SoundWire | | | ID 0 | | Controller | | +--------------------+ | | | | Link 0 +----+ +-------------------+ | | | Left Speaker Amp | | Link 1 | +--->| Maxim MAX98363 | | | | | ID 0 | | Link 2 +----| +-------------------+ | | | | Link 3 | | +-------------------+ | | | | Right Speaker Amp | +------------------+ +--->| Maxim MAX98363 | | ID 1 | +-------------------+ This was tested by booting the firmware and dumping the SSDT table to ensure that all SoundWire ACPI devices are created as expected with the properties that are defined in coreboot under \_SB.PCI0: HDAS - Intel Meteor Lake HDA PCI device HDAS.SNDW - Intel Meteor Lake SoundWire Controller HDAS.SNDW.SW00 - Cirrus Logic CS42L42 - Headphone Codec HDAS.SNDW.SW20 - Maxim MAX98363 - Left Speaker Amp HDAS.SNDW.SW21 - Maxim MAX98363 - Right Speaker Amp BUG=b:269497731 TEST=Verified SSDT for SNDW in the OS. Playback and recording are also validated on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e11dc642ff686ba7da23ed76332f7f10e60fade Reviewed-on: https://review.coreboot.org/c/coreboot/+/73280 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/brya/acpi: FBVDD_PWR_EN should be inverted on AgahTarun Tuli
The FBVDD_PWR_EN signal should be inverted in its control level on Agah v.s. Hades. The original change covered the Hades implementation, but needs to be updated to invert for Agah. This change can be removed once we drop support for Agah. BUG=b:280467267 TEST=built for Hades and Agah Change-Id: I7f90c03b8d9b859004e5c124bf0a1f7b59921c3d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75530 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-31Documentation: Document a Broadwell refcode modIru Cai
Document how to modify the Broadwell refcode to support the Intel GbE device. Change-Id: I4f4f1e1c4ec2d79b3eb9f9c35fdc0330208e8509 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75418 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/nissa/var/uldren: Fine tune eMMC DLL settingsDtrain Hsu
Fine tune eMMC DLL settings based on Uldren board. BUG=b:280120229 TEST=executed 2500 cycles of cold boot successfully on all eMMC sku. Change-Id: I82a55a1fe17aa910eb02464df463603dcbbbef05 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75459 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/nissa/var/uldren: Add ACPI DmaProperty for WLAN deviceDtrain Hsu
Add ACPI DmaProperty for WLAN device. `is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:279676191 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I6d898a939aa0be31a671d2436a81c34f7a1ec030 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75460 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-31mb/google/skyrim: Add common_config.acp_configTim Van Patten
Add 'common_config.acp_config' to the device tree, so we have the correct pin configuration. BUG=b:225320579 TEST=USE=fwconsole emerge-skyrim ... ; verify 'devbeep' works in depthcharge console TEST=Boot into ChromeOS, verify YouTube sound works with internal speakers and headphone jack TEST=Boot into ChromeOS, verify microphone with Google Meet Change-Id: Ie2d79408104273d8a53214b683800fa0663c14d3 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-31cpu/x86/mp_init: Use clflush to write SIPI data back to RAMJeremy Compostella
Improve boot time performances by replacing the wbinvd instruction with multiple clflush to ensure that the SIPI data is written back to RAM. According to some experimental measurements, the wbinvd execution takes between 1.6 up and 6 milliseconds to complete. In the case of the SIPI data, wbinvd unnecessarily flushes and invalidates the entire cache. Indeed, the SIPI module is quite small (about 400 bytes) and cflush'ing the associated cache lines is almost instantaneous, typically less than 100 microseconds. BUG=b/260455826 TEST=Successful boot on Skolas and Rex board Change-Id: I0e00db8eaa6a3cb41bec3422572c8f2a9bec4057 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Suggested-by: Erin Park <erin.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75391 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-31soc/amd/picasso/acpi/sb_pci0_fch: replace Memory32Fixed with DWordMemoryFelix Held
This brings the ACPI code more in line with both what the new code for the AMD SoCs will do and also what the current Intel code does. This was mainly done to have a reduced delta to the new AMD domain resource handling functions to debug it, but it might still be useful to upstream this change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cca05976b1c9d4e994e407b8c0197da7dd35eb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-31mb/msi/ms7d25: Add console die notificationMichał Żygowski
Add beeps and blink SATA LED on critical errors. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I45b8b4fda00d58a1ab1d7dfab49d6f841bc0b000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69821 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31payloads/edk2: Only pass IA32 argumentSean Rhodes
With the coreboot build process, `UniversalPayloadBuild.sh` calls `UniversalPayloadBuild.py`. That Python script will unconditionally build DXE as 64-bit, but accepts an argument for the entry point: parser.add_argument('-a', '--Arch', choices=['IA32', 'X64'], help='Specify the ARCH for payload entry module. Default build X64 image.', default ='X64') Currently, ` -a IA32 -a X64` is passed, and the Python script will use the `X64` argument, resulting in a payload that won't work with coreboot. Remove the `-a X64`, so the resulting build is a 32-bit entry point, and 64-bit DXE, which works with coreboot. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a557d6e155a2938b44036d98f9274cc8b38f156 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73668 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-05-31Makefile.inc: Create function to add a file to CBFSMartin Roth
This function can be called to more easily add a file to CBFS. Additional file attributes can be added later: cbfs-files-y += pagetables pagetables-file := $(objcbfs)/pt pagetables-type := raw pagetables-compression := none pagetables-COREBOOT-position := $(CONFIG_ARCH_X86_64_PGTBL_LOC) becomes $(call add-cbfs-file-simple, pagetables, $(objcbfs)/pt, raw, none ) pagetables-COREBOOT-position := $(CONFIG_ARCH_X86_64_PGTBL_LOC) This is especially useful inside macros where you may want to add an unknown number of entries. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I72bb2f21fb22f650b7970c7a37a48c10a4af0ed5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-31Makefile.inc: Remove duplicated -Wreturn-type optionElyes Haouas
"-Wall" turns on "-Wreturn-type". Change-Id: Iad4d8465112e3ca89d7d78e391d52c2b2d5f37cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-30mb/google/myst: Fix the DRAM Strap IDKarthikeyan Ramasubramanian
Incorrect memory part was used in CB:74745 to generate the DRAM Strap ID. Amend the memory_parts_used.txt and regenerate the DRAM Strap ID. BUG=b:272746814 TEST=Generate the DRAM Strap ID. Change-Id: I0668d7e02345610a11f9113d8bbe99a474f33f1a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-30acpi/acpigen: rename and clarify bus/IO/MMIO resource producer functionsFelix Held
The acpigen_resource_[bus_number,io,mmio*] functions didn't make it very clear that they are generating resource producer ranges and not resource consumer ranges. To clarify this, change the function names to acpigen_resource_producer_[bus_number,io,mmio*] and explicitly add the ADDR_SPACE_GENERAL_FLAG_PRODUCER flag which evaluates to 0, so this doesn't change the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I334f38aa8ab418d5577f92b980ff750504e2bb4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-30soc/amd/phoenix/Kconfig: use lower case hex digits in VGA_BIOS_IDFelix Held
cbfs_boot_map_optionrom will generate lower case hex digits for the filename to look for in CBFS, so make sure that the file name will use lower case hex digits and no upper case hex digits. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d4daa04120de0f2c853a44691b7e2c52eb2af20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75483 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-29util/crossgcc: Update nasm from 2.15.05 to 2.16.01Elyes Haouas
Timeless build for QEMU (i440fx/piix4) does not modify the binary. New patch is add to fix the build in a separate directory from the source. Change-Id: Ib69437be8ee69ad62fb1dfbbafabc2c4c885b7b2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-29mb/google/rex: Update GPIO PAD as per Proto 2 schematicsSubrata Banik
BUG=b:283477280 TEST=Able to build and boot google/rex as per Proto 2 schematics dated 05/16. +-----------------+------------------------------------+---------------------------+--------+ | GPIO | In Proto 1 | In Proto 2 | Impact | +-----------------+------------------------------------+---------------------------+--------+ | GPP_C01 | SOC_TCHSCR_RST_L | SOC_TCHSCR_RST_R_L | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_D19 | NC | EC_SOC_REC_SWITCH_ODL | Y | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E04 | HPS_INT_L | SOC_PEN_DETECT | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E17 | EN_HPS_PWR | EN_PP3300_SPARE_X | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F13 | GSPI1_SOC_MISO | GSPI1_SOC_MISO_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F21 | GPIO_F21_SPI_CS_L | SPI_SOC_CS_UWB_L_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H00 | GPIO_H00_SPI_CLK_R | SPI_SOC_CLK_UWB_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H01 | GPIO_H01_SPI_MOSI_R | SPI_SOC_DO_UWB_DI_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H02 | GPIO_H02_SPI_MISO | SPI_SOC_DI_UWB_DO_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S00 | UNNAMED_8_METEORLAKEU_I137_GPPS00 | SDW_HP_CLK_WLAN_PCM_CLK | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S01 | UNNAMED_8_METEORLAKEU_I137_GPPS01 | SDW_HP_DATA_WLAN_PCM_SYNC | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S02 | UNNAMED_8_METEORLAKEU_I137_GPPS02 | DMIC_SOC_CLK0_WLAN_PCM_OUT| N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S03 | UNNAMED_8_METEORLAKEU_I137_GPPS03 | DMIC_SOC_DATA0_WLAN_PCM_IN| N | +-----------------+------------------------------------+---------------------------+--------+ Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a8c43b0f845d3446188b7c926e482f91e5b45aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75407 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-28docs/releases/4.21: Add toolchain updatesElyes Haouas
Change-Id: Ibd7c23a8c7c30ff19e0564d01489fecb3f34dadc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75414 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-28mb/ibm: Add 4 SPR sockets server board IBM SBP1Patrick Rudolph
The IBM SBP1 is an evaluation platform. It's utilising: - 4 SPR sockets, having 16 DIMMs each - 240C/480T at maximum - 32x CPU PCIe slots - 2x M.2 PCH PCIe slots - Dual 200Gbit/s NIC - SPI TPM It has an AST2600 BMC for remote management. It doesn't have: - External facing USB ports - Video outputs - Audio codec Test: The board boots to Linux 5.15 with all 480 cores available. All PCIe devices are working and no errors in ACPI. All 64 memory DIMMS are working and M.2 devices can be used. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73392 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-28soc/intel/xeon_sp: Enable build for IO MarginingNaresh Solanki
This commit enables the build for IO Margining, ensuring that ASPM is disabled and certain FSP knobs are adjusted in coreboot as below 1. Enable DFXEnable 2. Disable PcieGlobalAspm 3. Disable KtiLinkL1En & KtiLinkL0pEn Since the FSP UPD does not provide all the necessary knobs for IO Margining, the following settings need to be applied during the FSP build process: 1. Enable PcdBiosDfxKnobEnabled 2. Disable PchDmiAspm 3. Enable SataTestMode 4. Enable WmphyMargining 5. Disable IioErrorEn TEST=Build for IBM sbp1 board. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-28commonlib/bsd/tpm_log_defs.h: replace macro with enumHimanshu Sahdev
replace multiple existing EV_* defines with enum ec_enum. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: Id58fc12134915cbeb41cccb54aae9bc3f7dde4b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75324 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-28Docs/releases: Fix table in 4.20 release notesNicholas Chin
The list of outstanding issues on ticket.coreboot.org is formatted as a Markdown table, which is not supported by Recommonmark. Reformat it as an embedded reStructuredText table. Change-Id: Id885e268d55348a365e38c536aed17f974f47840 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75463 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-27util/ifdtool: Add support for Intel 800 series chipsetSubrata Banik
This commit adds support for Intel 800 series chipset. The new chipset can be uniquely identified by its SPI speed, eSPI speed, and chipset name. This commit message is clear and concise, and it accurately describes the changes that were made to the code. It also includes the following information: - Specify the correct chipset name. "PCH Revision: 800 series Meteor Lake" - Show the valid eSPI/EC frequency. "Read eSPI/EC Bus Frequency: 20MHz" Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I70619d9e3ed2bcad86f84a0527e3a0ad13acd706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-27mb/google/rex: Update FMD to incorporate ISH firmwareSubrata Banik
This patch adds two new chromeos_*.fmd files for release and debug FSP builds targeting rex_ec_ish. `rex_ec_ish` variant would pack ISH firmware into the CSE boot partition hence, the blob size is expected to increase. Creates separate flash map layout to ensure ISH work is not impacting on the regular `rex0` project SPI flash usage. BUG=b:284254353 TEST=Able to build google/rex_ish_ec board and boot on target hardware. Change-Id: Ife4663d3ccf80a928646eadaac4c9ab49ad29055 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75471 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-27mb/google/rex: Create variant to support ISH enablementSubrata Banik
This patch creates a new variant to support the ISH enablement using Rex platform.The idea here is to leverage the `rex0` code as much as possible and add specific support for ISH enablement as per the hardware schematic differences. BUG=b:284254353 TEST=Able to build google/rex_ish_ec board and boot on target hardware. Change-Id: I625fd0b31aed998f4e8f2d139827bc212ee8a90b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75470 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-27soc/amd/common/block/psp: Unmap EFS region after useKarthikeyan Ramasubramanian
EFS header is mapped during PSP verstage and bootblock to read some SPI configuration. After use it is left unmapped. Unmap the EFS region after use. BUG=b:240664755 TEST=Build and boot to OS in Skyrim with unsigned PSP verstage. Change-Id: I865f45a3d25bc639eb8435b54aa80895ec4afd27 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75455 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-27soc/amd/mendocino/psp_verstage: Fix pending mapsKarthikeyan Ramasubramanian
cbfs_unmap does not unmap the mapped region from the boot device. This leads to some resource leaks eg. TLB slots in PSP. Explicitly call rdev_munmap on the address mapped by cbfs_map. BUG=b:240664755 TEST=Build and boot to OS in Skyrim with unsigned PSP verstage. Change-Id: I51b9d066a40103f2ebdf2ef2fc3da13beb467921 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-27soc/amd/common/psp_verstage: Fix pending mapsKarthikeyan Ramasubramanian
cbfs_unmap does not unmap the mapped region from the boot device. This leads to some resource leaks eg. TLB slots in PSP. Explicitly call rdev_munmap on the address mapped by cbfs_map. BUG=b:240664755 TEST=Build and boot to OS in Skyrim with unsigned PSP verstage. Change-Id: If1d355972cc743b8d8c451e1b3f827abd15e98fe Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-27soc/amd/common/psp_verstage: Fix build for FMAP without RW slotsKarthikeyan Ramasubramanian
On FMAP without RW slots, PSP verstage fails to build because of reference to FMAP_SECTION_FW_MAIN_A_*. Instead extract the offset and size of relevant sections using fmap_locate_area(). BUG=b:240664755 TEST=Build and boot to OS in Skyrim with unsigned PSP verstage. Change-Id: I29997534c6843b47a36655431f79e5c70bd17f9b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-27libpayload;arch,cpu/x86: drop USE_MARCH_586 Kconfig optionFelix Held
Only the Intel Quark SoC selected this option and that SoC was dropped in commit 531023285ea4 ("soc/intel/quark: Drop support"), so drop this Kconfig option too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4f1c7530cd8ac7a1945b1493a2d53a7904daa06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75473 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-27payloads/libpayload/configs: drop config.galileoFelix Held
The Galileo board was dropped in commit 037c25d4dd8d ("mb/intel/ galileo: Drop support"), so also drop this config file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8c85dc03c3a4a016d6e13f1bee170d1bc6439470 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75472 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-05-27cpu/intel/haswell: Add Broadwell Trad µcode updatesAngel Pons
Include µcode updates for Broadwell Trad(itional) CPUs. Tested on Asrock Z97 Extreme6 with an i5-5675C, µcode update loads: CPU id(40671) ucode:00000022 Intel(R) Core(TM) i5-5675C CPU @ 3.10GHz Change-Id: I54bb2e767f008b21dcf5d176f8b92a56dcabd129 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-05-26commit-msg: Match the Signed-off-by line with name and mail addressZheng Bao
The previous regular expression only matches the line starting with "Signed-off-by:". If the name and mail address are missing, it can not find out. The following words should be "name <mail@xxx.com>". Change-Id: I42cc399e79b65928a6aef87c51e5476c7158d166 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-26superio/common: Support more than one SuperIO in ACPIJonathon Hall
The SuperIO ACPI name was hard-coded to "SIO0". Allow setting the name in the device tree so more than one SuperIO can be named. An upcoming board (purism/librem_l1um_v2) has two SuperIOs - one in the AST2500 BMC, and a Nuvoton NCT6791D used for hardware monitor, POST display, etc. Many boards have references to SIO0 already, so the default name is still the same for a single SuperIO. Change-Id: Ibfa6ab7622749e6310ee91530bc3722e8e28d9bb Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75089 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26mb/google/rex/variants/baseboard/rex: Add CPU power limit valuesSumeet Pawnikar
Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for rex baseboard. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values as below log message for 15W SKU on Rex board. Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (57000, 57000) PL4 (W) (114) Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-26soc/intel/common: Support power limits update for variantsSumeet R Pawnikar
Add support to update power limit values for variants. Until now, each SoC implements this themselves. To avoid code duplication, add this to common code. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values as below log message for 15W SKU on Rex board. Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (57000, 57000) PL4 (W) (114) Change-Id: I414715f211d816bbfad03a673ca96dd5df94caeb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-26mb/google/rex: Set frequency and gears for SaGv pointsBora Guvendik
Restrict memory speed to 6400 MTS as per board design. BUG=b:282164577 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3dec383c7c585b80a73089f3403011c5cda61f65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-26soc/intel/meteorlake: Hook up SaGvFreq, SaGvGear updsBora Guvendik
Hook the SaGvFreq, SaGvGear upds so that mainboard can change the settings via devicetree. Meteor Lake supports 4 SaGv work points and it can dynamically scale the work point based on memory bandwidth utilization. Dynamic gearing technology allows the Memory Controller to run at 1:1, 1:2 or 1:4 ratio of DRAM speed. The gear ratio is the ratio of DRAM speed to Memory Controller Clock. BUG=b:282164577 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I37169880af4019675374594e90735b5d7d0873b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75290 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 00:24:53 +0000