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2022-09-07util/lint/lint: Add -I option to invert test resultsMartin Roth
To test the linters, we want to invert the results so that any test that passes shows up as a failure. This will allow us to verify that all of the linters are working correctly. This will be tested nightly as well as on changes to the lint tools. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia8024c6ab0c91fd9f630f37dc802ed3bc6b4608c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-07soc/amd/mendocino/Kconfig: Enable APOB_HASHFred Reitberger
Enable the APOB_HASH feature. This improves boot times by ~10ms. BUG=b:193557430 TEST=boot to OS and verify boot time improvement Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9628b67cd3206ffdbef23162c453dc183c69e5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67377 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07soc/amd/common/block/apob: Add hashed APOB supportFred Reitberger
Comparing the APOB in RAM to flash takes a significant amount of time (~11ms). Instead of comparing the entire APOB, use a fast hash function and compare just that. Reading, hashing, and comparing the hash take ~70 microseconds. BUG=b:193557430 TEST=compile and boot to OS in chausie with and without this option set Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I241968b115aaf41af63445410660bdd5199ceaba Reviewed-on: https://review.coreboot.org/c/coreboot/+/67301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-07lib/xxhash.c: Add new hash functionsFred Reitberger
Add xxhash functions. This is a very fast hash function, running at RAM speed limits. This code was adapted from the linux kernel with minor modifications to make it fit in coreboot. BUG=b:193557430 TEST=compile Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I8108af5ab14d8e6c6f5859bd36155c7d254e892c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-07tests/commonlib/rational-test: Use test group runner wrapperJakub Czapiga
coreboot unit-tests framework requires tests to use cb_run_group_tests() instead of cmocka_run_group_tests() for Jenkins to work correctly. Wrapper ensures that each test has its own report file and does not overwrite results of other tests. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iead63cab0465f37b2da0c7b3ef256057e3a191a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67371 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07util/spd_tools: Update LP5X support for ADL/RPL/MTLCaveh Jalali
This updates the SPD utility and generated SPDs for LP5X to use memory type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on Intel Tech Advisory Doc ID #616599 dated May 2022, page 15. SPDs were regenerated with: "util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5" This only affects the SPDs for 2 memory parts for Intel SoCs and the only board referencing these is rex. BUG=b:242765117 TEST=inspected SPD hex dump Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-07amd: Convert dptc_enable to boolTim Van Patten
dptc_enable is being treated as a bool, so convert to explicitly be a bool. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim Change-Id: I0e93d892b3b8016221812c8b9ec6c257dcf13ef5 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67188 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50Werner Zeh
Due to layout restrictions on mc_ehl2, the SD-card interface is limited to operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not supported. Limit the capabilities in the SD card controller to DDR50 mode only so that the SD card driver in OS will choose the right mode for operation even if the attached SD card supports higher modes. Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-07mb/siemens/mc_ehl2: Set I2C bus 1 speed to 100 kHzWerner Zeh
Since the new RTC is located in I2C bus 1 now, set the bus speed to 100 kHz as well. Change-Id: Ica9468e559bc654545592a9b4d23f3164eafca8a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67102 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07mb/siemens/mc_ehl2: Change to new RTC RV3028-C7Werner Zeh
Since the latest redesign a new RTC was introduced on mc_ehl2. Instead of the old RX6110SA the new Micro Crystal RTC RV3028 is used now. Since the address of this new RTC conflicts with an EEPROM on I2C bus 2, the new RTC was moved to I2C bus 1. As the mainboard is not finished yet, there are no incompatibility issues with this change. Every new mainboard will have the new RTC and the older mainboards are not delivered yet. Change-Id: I3dd00855b8c9b22bdea21d3c8563cdb392868751 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-07mb/siemens/mc_ehl: Move RTC Kconfig option to variant levelWerner Zeh
With a redesign of mc_ehl2 the used RTC was changed. In order to be able to select a different RTC type for every variant move the RTC Kconfig switch into the variant's Kconfig file. Change-Id: Ia24703ede6a935e3b9886df87237857baec7d6a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67100 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07drivers/i2c: Add a new RTC RV-3028-C7 from Micro CrystalWerner Zeh
This patch adds a driver for a new RTC from Micro Crystal. Supported features are: * configure backup voltage switchover via devicetree * configure backup capacitor charging mode via devicetree * set date if a voltage drop on backup voltage was detected to either a user definable (devicetree) or coreboot build date Change-Id: I37176ea726e50e4e74d409488981d7618ecff8bb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-07Update arm-trusted-firmware submodule to upstream masterYidi Lin
Updating from commit id e0a6a512b: 2022-02-03 22:59:34 +0100 - (Merge changes from topic "msm8916" into integration) to commit id 7805999e6: 2022-09-05 16:42:34 +0200 - (Merge changes from topic "st-nand-updates" into integration) This brings in 1030 new commits. Change-Id: I981956fbdcbcfa4ce185652478b9bb30d40f5686 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-07mb/google/geralt: Pass reset gpio parameter to BL31Bo-Chen Chen
Pass the reset gpio parameter to BL31 to support SoC reset. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifdfbd6bd82f64b084f6349cb617443053c89a3f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67357 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07soc/mediatek: a common implementation to register BL31 resetHung-Te Lin
The implementations of register_reset_to_bl31() are the same for MedaiTek platforms, so we extract them to soc/common/bl31.c. BUG=None TEST=build pass Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-07soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxesJohnson Wang
Some of the pll settings are incorrect, which cause problems in GPU after booting into kernel. - MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix it to enable MFGPLL properly. - Switch SPMI clock muxes to 260M to avoid kernel hang while probing SPMI kernel driver. TEST=GPU bringup correctly. BUG=b:233720142 Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67355 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2022-09-07mb/google/corsola: Fix ANX7625 power-on T4 sequenceZanxi Chen
The T4 of ANX7625 power on sequence should be larger than 0ms, but it's -59ms now. So add 70ms delay between DSI_TE and LCM_RST. BUG=b:242352915 TEST=The sequence T4 is larger than 0ms when power on. Change-Id: I6b888707ec3c0612e396564e77c4cdbe92614dc5 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-06mb/google/skyrim/var/winterhold: Update devicetree settingEricKY Cheng
Initialize winterhold devicetree. BUG=b:241196632 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-06lint/checkpatch: Fix incorrect camelcase detection on numeric constantElyes Haouas
This reduce the difference with linux v6.0-rc3. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I15e1a935665c38b8a2109d412b1d16f935cbb402 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-06util/lint/lint-stable-019-header-files: add testMartin Roth
Add a test to make sure that the linter fails correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I971951d4248dd10abe4c622025fdaf86e014c6cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06util/lint: Add rules.h & compiler.h to 019-header-files linterMartin Roth
The rules.h & compiler.h includes were removed in previous commits, so add the checks to keep them out to the linter. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06src/soc/intel: remove force-included header compiler.h from fileMartin Roth
The header file `compiler.h` is automatically included in the build by the top level makefile using the command: `-include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h`. Similar to `config.h`, 'kconfig.h`, and 'rules.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06src: remove force-included header rules.h from individual filesMartin Roth
The header file `rules.h` is automatically included in the build by the top level makefile using the command: `-include src/soc/intel/common/block/scs/early_mmc.c`. Similar to `config.h` and 'kconfig.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67348 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-06mb/hp/z220_series: Add configs for integrated XHCIBill XIE
Without these, all SuperSpeed ports are wired to EHCI #2. "superspeed_capable_ports" and "xhci_switchable_ports" should fit both CMT and SFF variants, while "xhci_overcurrent_mapping" should be consistent with the first 4 elements of mainboard_usb_ports[]. With this commit, SuperSpeed devices plugged in SuperSpeed ports are wired to the XHCI on my own Z220 SFF. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67089 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-06configs/config.prodrive_hermes: Fix typoAngel Pons
Remove extra 'o' in "Tech*o*nologies". Change-Id: Icf24e00fb895a670ea798f64a79035d858ec0d4f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06mb/google/skyrim/var/winterhold: Add gpio override settingsEricKY Cheng
Follow FT6_SOC_GPIO_PM&Strap_20220815A.XLSX update Gpio setting BUG=b:240824497 BRANCH=None Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2086c326cbf46ba6378d18d37dcbbe9fafa6b2bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-06Makefile.inc: Fix build hang if file-size is run on empty stringMartin Roth
Currently, if for some reason, the file-size command is called on an empty string, the build will hang waiting for stdin input to cat. Since wc accepts a file, this cat was unnecessary anyway. Put the file name in quotes so an empty string will result in calling wc on an actual null file instead of just leaving the filename blank. This results in an error, and will probably halt the build. BUG=214790407 TEST=Build default build. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I3dacf1968ed897a8ebd00f95583c2f254a7fb55a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-06allocator_v4: Disable top-down mode by defaultNico Huber
The top-down allocation feature was merged prematurely before platforms that don't report their resources correctly were fixed. Let's turn it off by default. Change-Id: I982e6d7355b9e689de10357d6c16ed718705270e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-09-05util/lint: ignore util/goswid, a new submoduleMartin Roth
git submodules should be ignored when parsing the coreboot tree for lint errors. Those should be handled in their own commit checks. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I62b58f0c536312fe4677855bca8f44bc7d3ebc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-05Revert "allocator_v4: Treat above 4G resources more natively"Nico Huber
This reverts commit 117e436115484f0ce184114b22b716616592e77e. Depends on top-down allocation to keep the behavior to place hot-plug reservations above 4G. The latter was merged prema- turely, though. Change-Id: I5721cb84b29fc42240dff94f49a94461d88e7fbc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67329 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-05soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei ModuleSubrata Banik
This patch fixes a hidden issue present inside FSP-S while coreboot decides to skip performing MP initialization by overriding FSP-S UPDs as below: 1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need to use coreboot wrapper for performing any operation over APs. 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided to skip FSP running CPU feature programming. Unfortunately, the assumption of coreboot is not aligned with FSP when it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of the APs (Application Processors) upon passing `NULL` pointer to the `CpuMpPpi` FSP-S UPD. FSP-S creates its own infrastructure code after seeing the CpuMpPpi UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker` to perform those additional initialization which is not relevant for the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid running CPU feature programming on APs). Additionally, FSP-S binary size has increased by ~30KB (irrespective of being compressed) with the inclusion of the CpuMpPei module, which is eventually not meaningful for coreboot. Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD and avoid APs getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. Ideally, FSP should have avoided all AP related operations when coreboot requested FSP to skip MP init by overriding required UPDs. TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on Google/Redrix, Kano, Taeko devices with SkipMpInit=1. Without this patch: Here is the CPU AP logs coming from the EDK2 (open-source) [UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the CpuMpPpi UPD. [SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6 [SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2 CpuMpPei.efi PROGRESS CODE: V03020002 I0 [SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE [SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 76FA0239 AP Loop Mode is 2 GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found. CPU[0000]: Microcode revision = 00000000, expected = 00000000 [SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6 Does not find any stored CPU BIST information from PPI! APICID - 0x00000000, BIST - 0x00000000 [SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97 [SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA [SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A PROGRESS CODE: V03020003 I0 With this patch: No instance of `CpuMpPei` has been found in the AP UART log with FSP debug enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ebe0bcfda513e79e791df7ab54b357aa23d295c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66706 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-05ec/google/chromeec: Modify ufp from type-c roleDtrain Hsu
In order to fix the USB port of type-C dongle has no function after reboot/shutdown, modify ufp which is in google_chromeec_usb_pd_get_info from the bit1 of type-c role (PD_CTRL_RESP_ROLE_DATA). BUG=b:239138412 TEST=Built coreboot image and verified that using this patch can detect usb drive after reboot. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I73a4a6ec37129388783599125f067068d155d93f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67168 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04mb/google/rex: Correct GPSI0 muxing for pads requiring NF8Tarun Tuli
GSPI0 pads required muxing to NF8. Support for extended native functions was added in commit b6c32d7fe4ea98ba8b3a10cb5ce46448801855b8 BUG=b:244610269 TEST=build and booted on Rex Change-Id: Iab4e0bc6890cd8e976c513fe87dda0da9b5f2ee0 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2022-09-04util/amdfwtool/amdfwread: Fix incorrect option indexKarthikeyan Ramasubramanian
index I/O argument to getopt_long is not the index to argv. Instead it is an index into the optlong array corresponding to the parsed option. Also getopt() uses a global variable optind to track the index of the next argument to be processed. Use the optindex variable as an index to extract the filename from argv. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Change-Id: I33c74a0c8e12c5af76954524cf7294b7541d286b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66553 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04util/spd_tools: Rebuild utils when source changesCaveh Jalali
This adds source file dependencies to utilities so that they are rebuilt when the source is changed. Previously, binaries were only built if they did not already exist and never rebuilt to reflect source file changes. BUG=none TEST=verified binaries are rebuilt when source files are touched. Change-Id: I4775fe0e00e0f5d4f8b4b47331d836aba53c0e69 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-04drivers/intel/dptf: Add multiple fan support under dptfSumeet Pawnikar
Add multiple fan support for dptf policies BUG=b:235254828 BRANCH=None TEST=Built and tested on Redrix system for two fans Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-04mb/google/brya/var/ghost: Delete variantJack Rosenthal
This project concluded and the coreboot implementation is no longer required. BUG=b:244596639 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67299 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04util/lint: Add lint tests to make sure they fail correctlyMartin Roth
Change-Id: I1ff3302acdd5bc5d17a5d394d953b6877750b6a6 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-04mb/google/dedede/var/shotzo: Update DPTF parametersTony Huang
Update DPTF parameters from internal thermal team. BUG=b:244373677 BRANCH=firmware-dedede-13606.B TEST=Build image and verified by thermal team. Change-Id: I8415e0d25a79764f0c1d11688728b7caa3b3d6a4 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-04allocator_v4: Treat above 4G resources more nativelyNico Huber
We currently have two competing mechanisms to limit the placement of resources: 1. the explicit `.limit` field of a resource, and 2. the IORESOURCE_ABOVE_4G flag. This makes the resource allocator unnecessarily complex. Ideally, we would always reduce the `.limit` field if we want to "pin" a specific resource below 4G. However, as that's not done across the tree yet, we will use the _absence_ of the IORESOURCE_ABOVE_4G flag as a hint to implicitly lower the `limit` of a resource. In this patch, this is done inside the effective_limit() function that hides the flag from the rest of the allocator. To automatically place resources above 4G if their limit allows it, we have to allocate from top down. Hence, we disable the prompt for RESOURCE_ALLOCATION_TOP_DOWN if resources above 4G are requested. One implication of the changes is that we act differently when a cold-plugged device reports a prefetchable resource with 32-bit limit. Before this change, we would fail to allocate the resource. After this change, it forces everything on the same root port below the 4G line. A possible solution to get completely rid of the IORESOURCE_ABOVE_4G flag would be rules to place resources of certain devices below 4G. For instance, the primary VGA device and storage and HID devices could be made available to a payload that can only address 32 bits. For now, effective_limit() provides us enough abstraction as if the `limit` would be the only variable to consider. With this, we get rid of all the special handling of above 4G resources during phase 2 of the allocator. Which saves us about 20% of the code :D Change-Id: I4c7fcd1f5146f6cc287bd3aa5582da55bc5d6955 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65413 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04pciexp_device: Propagate above-4G flag to all hotplug devicesNico Huber
The `IORESOURCE_ABOVE_4G` flag was only explicitly set for our dummy device that reserves resources behind a hotplug port. The current re- source allocator implicitly extends this to all devices below the port, including real ones. Let's make that explicit, so future changes to the allocator can't break this rule. Change-Id: Id4c90b60682cf5c8949cde25362d286625b3e953 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66719 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-04allocator_v4: Introduce RESOURCE_ALLOCATION_TOP_DOWNNico Huber
Add option to resource allocator v4 that restores the top-down allocation approach at the domain level. This makes it easier to handle 64-bit resources natively. With the top-down approach, resources that can be placed either above or below 4G would be placed above, to save precious space below the 4G boundary. Change-Id: Iaf463d3e6b37d52e46761d8e210034fded58a8a4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-04mb/prodrive/hermes: Use snake case for identifiersAngel Pons
There's no reason to use camel case for EEPROM region names or local variables. Use snake case for consistency with coreboot's code style. Change-Id: Id1200a0c778095b109d824a1ca4e3e69591e4165 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-04vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00Saurabh Mishra
Update generated FSP headers for Alder Lake N from v3267.01 to v3301.00. Changes include: - FspsUpd.h: 1. Add VccInAuxImonSlope UPD 2. Update UPD Offset in FspsUpd.h BUG=b:242152105 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa. Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb526e8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-04device/i2c_bus: Add routines to read and write multiple bytesWerner Zeh
Some devices require that several bytes are written with a single I2C write command. Extend the i2c_bus interface functions and add both, read and write for more than one byte at a defined byte offset. Change-Id: I0eec2e1d4185170f02b4ab35aa6546dc69569303 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67098 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-04security/vboot/tpm: Avoid duplicate vb2api_secdata_firmware_create callsYu-Ping Wu
For TPM2, vb2api_secdata_firmware_create() is already called from setup_firmware_space() from _factory_initialize_tpm(). Therefore move the duplicate call from factory_initialize_tpm() to TPM1's _factory_initialize_tpm(). Change-Id: I892df65c847e1aeeabef8a7578bec743b639a127 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-03util/lint/lint: Reformat usageMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I684d374bd02a42e178383c26936e137e173f8f7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-03util/lint/lint: Add command line parsingMartin Roth
The lint script just did very basic argument parsing and required the sub-command and --junit argument to be in specific locations. I'm adding additional commands, so the first step is to add true command line parsing. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7118c29e6c5d785b35a7ae12cf5984c43ebc3ab9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67191 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-03soc/intel: Add SI_DESC region to GSCVD rangesJulius Werner
Intel platforms have soft straps stored in the SI_DESC FMAP section which can alter boot behavior and may open up a security risk if they can be modified by an attacker. This patch adds the SI_DESC region to the list of ranges covered by GSC verification (CONFIG_VBOOT_GSCVD). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0f1b297e207d3c6152bf99ec5a5b0983f01b2d0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-02cbfs/vboot: Adapt to new vb2_digest APIJulius Werner
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02util/docker/coreboot-jenkins-node: Install cmockaFelix Singer
flashrom uses cmocka for unit testing. Install it so that the CI can use it. Change-Id: I5c168e480d6f4cbfbbd175ecb035c88bfcbac00b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67272 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-02amdblocks/alib.h: Add DPTC parameter IDsTim Van Patten
Add additional DPTC parameter IDs that are necessary when throttling the SOC due to low/no battery. These additional parameters are used in later CLs. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I9e944d7c620414ec92d08a3d1173ba281d593ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67182 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-02mb/google/skyrim: Remove elog_gsmi_cb_mainboard_log_wake_sourceRaul E Rangel
elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes eSPI transactions. If the SMI interrupts an ongoing eSPI transaction from the OS it will conflict and cause failures. Removing this call to avoid conflicts. This can be re-enabled after refactoring google_chromeec_get_mask to use ACPI MMIO. This is a copy of CB:63280 but for skyrim. BUG=b:227163985, b:243557044 TEST=suspend/resume skyrim and no longer see EC wake sources in elog. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iac56840fe15101bc556d8cce9960f761c6ea7181 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-09-02mb/google/rex: Enable DSP UPDEric Lai
Enable DSP setting. Make sure the SSP can work as expected. BUG=b:243123156 TEST=Dev beep working on Rex. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I6ae28e414ac4ac33f596df57691c979eac5fe132 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67270 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-02soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enablingSubrata Banik
Enabling Bus Master isn't required by the hardware, so we shouldn't need to enable it at all. However, some payloads do not set this bit before attempting DMA transfers, which results in functionality failure. For example: in this case, unable to see the developer screen in Depthcharge. In the prior IA SoC platform, FSP/GFX PEIM does the BM enabling for the IGD BAR resources but starting with the MTL platform, it fails to do so resulting into inability to see the Pre-OS display. BUG=b:243919230 ([Rex] Unable to see Pre-OS display although GFX PEIM Display Init is successful during AP boot) TEST=Able to see the developer screen with eDP/HDMI while booting the Google/Rex. Also, this change doesn't impact the previous platforms (ADL, TGL, CML etc.) where the BM is default enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-01Documentation: Move devicetree documentationMarc Jones
Move devicetree.md from acpi/ to getting_started/. The devicetree has nothing to do with ACPI and getting_started has the most similar information about coreboot. Change-Id: I873b293f036a9e3bcdc98135386f9158c645513c Signed-off-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-09-01mb/google/guybrush: select SYSTEM_TYPE_LAPTOPMatt DeVillier
Select SYSTEM_TYPE_LAPTOP so the FADT PM profile is correctly set to mobile (vs the default of desktop). TEST=build/boot google/dewatt, run FWTS and verify FADT PM profile correct Change-Id: I480fbe85782e2c63efa8d2212d503a47d8149ab9 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-01mb/google/skyrim: Add missing USB ports to device treeRaul E Rangel
As part of investigating b/240690391 I noticed that we were missing the daughter board ports. Not all SKUs have these ports connected, but it doesn't hurt to have the extra ACPI nodes. BUG=none TEST=build Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id6fc34acbfa30bc15e697043bf93bcf584256128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-09-01drivers/elog/gsmi.c: Fix compiling for 64bitArthur Heymans
Change-Id: Ic8e04ae043145a3633c0b8379a797724f95fd7ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-01amd/*/Makefile.inc: Put common words into common Makefile.incZheng Bao
Definition of FIRMWARE_LOCATION, POUND_SIGN, DEP_FILES, amd_microcode_bins are moved to common Makefile.inc. Change-Id: I5a0ea27002e09d0b879bafad37a5d418ddb4e644 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62658 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-09-01x86/cache.c: Implement dcache_*Hsin-Te Yuan
A new ChromeOS automated test will be introduced to check the cbmem log of diagnostic boot mode. Because the diagnostic boot does not allow booting into kernel, the test must perform AP reset and then check the cbmem log afterwards. However, the memory content might not be written back to memory (from CPU cache) during AP reset because of the cache snooping mechanism on x86. Hence, some API to flush cache is needed. Implement dcache_* to allow flushing cache proactively in x86. To avoid unnecessary flush, check dma_coherent before calling dcache_* functions, which will be always true in x86. Therefore, this change won't affect the original functionality. BUG=b:190026346 TEST=FW_NAME=primus emerge-brya libpayload Cq-Depend: chromium:3841252 Signed-off-by: Hsin-Te Yuan <yuanhsinte@google.com> Change-Id: I622d8b1cc652cbe477954a900885d12e6494d94d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-01vendorcode/intel/fsp2/glk: Add the FSP headers for version 2.2.3.1Sean Rhodes
Add the headers for 2.2.3.1, which includes the following changes over 2.2.0.0: • [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry failure in less than 5 cycles when a USB2 Ethernet Dongle is connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter 7.20.6 for new Register settings. • [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini Lake/Gemini Lake – R • [Update] MRC new version update to 1.38. • [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from S4 issue with latest Wifi driver. [Update] MRC new version update to 1.39. Included fix for MinRefRate2xEnable and support for Rowhammer mitigation. • [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This change specific to DDR4 memory configuration. • GLK Klocwork Fix • [Update] MRC new version update to 1.40. Added in a separate directory as the default. The 2.2.0.0 headers were left and will be used for Google boards, as some offsets have moved. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-09-01payloads/edk2: Remove architecture from build stringSean Rhodes
Whilst UefiPayloadPkg is always built with support for 32-bit and 64-bit, this is not the case for all edk2 targets. Move this to the build command so they can be specified on each target. Also add the `-s` switch, which stands for quiet to suppress edk2 printing War and Peace whilst building. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If94abd4e28917718c76ad5945966e7be668c8f61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66364 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-01payloads/edk2: Rename the update recipeSean Rhodes
Rename the update recipe, which updates the edk2 repository, to $(EDK2_PATH). There is no functional change here. This recipe must be phony so it runs every time. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I30fedbee7459b79a85a23678e0075368eda95da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66363 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-01payloads/edk2: Clone edk2 and its submodules in parallelSean Rhodes
When cloning edk2, download the submodules at the same time. There is no functional change here, just a minor speed improvement. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieeb481346093588bd8d237857966001dc81460b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66362 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-01payloads/edk2: Adjust the WORKSPACE targetSean Rhodes
First, remove the `-p` flag; as it's a file target it's not needed in this case. Second, remove the clone as this is handled in the update recipe. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3829a3151be2d05a067a160fa770e5eb7ad4aad4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66361 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-01payloads/edk2: Convert UefiPayloadPkg to a file targetSean Rhodes
Convert UefiPayloadPkg (UEFIPAYLOAD.fd) to a file target. There is no functional change here, it just avoids it being copied out of the build dir, into an output directory and then into build. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iff097f6f1e715c697c33c50c395d7c1b88cc6280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66360 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-01mb/google/brya/acpi: Save/restore/clear some registers over GC6Tim Wawrzynczak
Nvidia recommends saving and restoring the LTR Enable bit in PCIe config space for the PCIe root port before/after GC6 entry. Also the detectable error bit should be cleared, as there may be errors expected during the GC6 flow. BUG=b:214581763 TEST=no more correctable errors after GC6 entry/exit Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I058ce1b3f17fb6cc59785a85efaf9ea0504cf2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/66808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-01mb/google/nissa: Mark PCIe wifi device as untrustedReka Norman
BUG=b:238937091 TEST=Dump SSDT on nereid and check that the wifi device contains the DmaProperty. Also check that the kernel marks the device as untrusted. Change-Id: I0725ea18d52420a3161d6fcfa3bcb72ebe35f3a5 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-31soc/amd/mendocino/Kconfig: select extended eSPI decode range supportFelix Held
Select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES and remove the TODO from SOC_AMD_COMMON_BLOCK_HAS_ESPI. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90e3bf3f196e22b428b01ea0437c1224702d2b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-31acpi: Replace EC_ENABLE_AMD_DPTC_SUPPORT with Kconfig valueTim Van Patten
Compile-time support of DPTC is controlled by EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. Each variant's run-time support of DPTC continues to be controlled by the variant's overridetree.cb "dptc_enable" value. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-31soc/intel/alderlake: Add new pcie5 alias for raptorlakeBora Guvendik
Pcie5_1 is added for DID 0xA72Dh and BDF 0/1/1. References: RaptorLake External Design Specification Volume 1 (640555) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Id7440bf202d5560ff92807877d48b94054cb1de9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-31mb/amd/chausie/Kconfig: Re-enable ESPI_RETAIN_PORT80Fred Reitberger
Chausie fails to boot without this option set. Enable in the mainboard rather than the SoC Kconfig to not impact Skyrim. TEST=boot to OS Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9f2a1be9eddb9e17407d00ff50ceb70a2718ce3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-31soc/mediatek/mt8188: Add SPM loader and initialize SPM in RAM stageRex-BC Chen
Add support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. SPM is an essential component on MediaTek SoC, so we initialize PPM in soc_init(). For MT8188, SPM will handshake with DPM to do initialization, so we need to call spm_init() after dpm_init(). This SPM flow adds 33ms to the boot time. firmware log: mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 25 msecs SPM: spm_init done in 33 msecs, spm pc = 0x400 TEST=spm pc is 0x400 which is in idle state. BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I1a1f49383e0ceadc259a18272fc1c277b65406ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/66973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek: Move some SPM functions to commonBo-Chen Chen
Some functions are the same in spm.c for MT8192, MT8195, MT8186 and MT8188, so we move them to common/spm.c. TEST=build pass. BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I29ddefc47d8bd156fa1ca0cedd4deaed676ae7e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek/mt8188: Use MHz as unit for current_clkBo-Chen Chen
The unit of current_clk in pmif_ulposc_check() should be MHz. We use pmif_get_ulposc_freq_mhz() to get the default hardware value in MHz. Without this modification, the judgement in pmif_ulposc_check() is alway wrong due to the wrong unit. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3bf80a23bb35ff657023eb4b7e009fa233f61244 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek/mt8188: Add DEVAPC basic driverNina Wu
Add basic DEVAPC (device access permission control) driver. DEVAPC driver is used to set up bus fabric security and data protection among hardwares. DEVAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DEVAPC driver. 1. Initialize DEVAPC. 2. Set master domain and secure side band. 3. Set default permission. TEST=check logs of DEVAPC ok. BUG=b:236331724 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Change-Id: Iad3569bc6f8ba032d478934ba839dc4b5387bafc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek: Move common DEVPAC enums and functions to commonBo-Chen Chen
Some enums and functions are the same in DEVAPC driver for MT8195, MT8186, and MT8188, so we move them to common folder. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia7d2145780780fd54b76952db96424b8ea477594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31device/dram/ddr4.c: note that dimm size calculation won't work for 3DSKrystian Hebel
Change-Id: I52548e544165b4732d9989da6455c8fd77bf99d3 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-31device/dram/ddr4.c: fill missing ECC info from SPDKrystian Hebel
Change-Id: I80fccfa6d108b68d6f33a3d47766205b423a41ff Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-31soc/mediatek/mt8188: Initialize DPM in ramstageXi Chen
Add initialization of DPM drvier for DRAM low power mode. DPM is an essential component on MediaTek SoC, so we initialize DPM in soc_init(). This DPM flow adds 22ms to the boot time. coreboot logs: CBFS: Found 'dpm.dm' @0x156c0 size 0xfc in mcache @0xfffdd110 mtk_init_mcu: Loaded (and reset) dpm.dm in 6 msecs (422 bytes) CBFS: Found 'dpm.pm' @0x15800 size 0x3c59 in mcache @0xfffdd140 mtk_init_mcu: Loaded (and reset) dpm.pm in 16 msecs (18910 bytes) TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I46baa7b49e90d53dd4d1d95af9c46622faf30419 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66969 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-31soc/mediatek/mt8188: Support 4 channel DRAM in DPM init flowXi Chen
TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: Ia68aca1d1e8729739246157904727123e5d001e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66968 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-31soc/mediatek/mt8188: Add DPM firmware filesXi Chen
DPM is a hardware module for DRAM power management, which is used for DRAM low power mode. TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I872396fe2c5accd92ba5c14b124125bd58257771 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66967 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-31soc/mediatek: Move dpm_4ch.c to commonXi Chen
MT8195 and MT8188 share the same dpm_4ch.c, so we move it to common folder. TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I13406707d3b331ced57af62f4ba4f365e9ac4f84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66966 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31allocator_v4: Completely ignore resources with 0 limitNico Huber
It seems pass 1 and 2 were inconsistent. The first would account for resources with a limit of 0 even though the second can't assign anything for them. Change-Id: I86fb8edc8d4b3c9310517e07f29f73a6b859a7c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65402 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-31mb/google/rex: Correct EC-is-trusted logicKapil Porwal
Fix EC_IN_RW config for Rex. Dauntless on Rex does not have an EC_IN_RW GPIO pin. Port of commit 7f339c6050c5 ("mb/google/corsola: Correct EC-is-trusted logic") BUG=b:243950850 TEST=Built and booted to Google Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I97e5c752b4f36c9221137903f755837880f6b1c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67208 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-31Revert "mb/google/rex: Disable LID_SHUTDOWN"Subrata Banik
This reverts commit 47fee08fc3a383e14dc974754d6e463fa320badf. The required EC changes are now in place to revert this W/A that disables the LID based shutdown. BUG=b:243920003 TEST=No shutdown request has triggered while booting AP at depthcharge. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5ae56912f030f6f0e3cb49282bbffc920fb389c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67206 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-31vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3301.03Selma Bensaid
The headers added are generated as per FSP v3301.03 In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:243693364 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: Idbd39ed53d4ba05248a0e83c104846960253931e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-30mb/google/skyrim: Fix APCB_SBR_D5.gen build rulesKarthikeyan Ramasubramanian
CB:66978 introduced an incorrect condition to check for the presence of SPD binaries to be injected into APCB_SBR_D5.gen. This caused the SPDs to be not injected into the APCB and hence the system fails to boot. Fix it by updating the path of the SPD binaries correctly. BUG=b:244173966 TEST=Build and boot to OS in Skyrim. Change-Id: I5efa634fafdcc4769dfad5f533d5512e7c03644f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-30.gitignore: Add .vscode/Tim Van Patten
Visual Studio Code uses the directory .vscode/ to store data, so add it to the .gitignore. Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I8fe6439f01bd5ada8ceb814a22602db241aa11d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-30soc/intel/cmn/block/acpi: Add new GPIO ASL MethodTim Wawrzynczak
Ths new Method, GSCI, allows control over whether or not IRQs are routed as SCI#s for the given GPIO. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic61caaf77d2c6e295e67a1501544e8b8fc6f3b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-30mb/google/nipperkin: Set BT enable_delay_ms to 10msRob Barnes
Override bluetooth enable_delay_ms to 10ms, per advise from vendor. BUG=b:233369179 BRANCH=guybrush TEST=Boot nipperkin, connect to headset, suspend and reboot, headset still functions. Change-Id: Ic00de6704018f27339512929f85531aa72205b0e Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67177 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-30mb/google/guybrush: Set BT enable_delay_ms to 200msRob Barnes
Set bluetooth enable_delay_ms to 200ms. 200ms is the lowest common denominator between the two BT chipsets. BUG=b:233369179,b:236289478 BRANCH=guybrush TEST=Connect to headset, suspend and reboot, headset still functions Change-Id: Id4c23de37351d28d02aaa797fa19ff49e9dfa76c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65180 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-30soc/intel/cmn/block/acpi: Modify GPIO Methods to use bitfieldsTim Wawrzynczak
IMHO, using bitfields directly in the Field declaration makes the ASL code more readable then directly manipulating the entire 32-bit dword. TEST=ACPI code using several of these Methods still works (google/agah dGPU ACPI code) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9909700022d8b55db3f5208010bdff11ddaf4e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66812 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-30mb/google/brya/variants/nivviks: Define DPTF policies for NirwenVidya Gopalakrishnan
Added DPTF passive, critical, active policies for Nirwen. Added additional TSR for Nivviks and updated the PL2 time window Ref: EDS doc#645550 BUG=b:238713292 TEST= Boot to OS and verify dptf policies are set based on fw_config. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Iae46736d8d7723a20983dcaad42a7007d76cfad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-30mb/google/nissa: Configure the DPTF policies based on fw_configV Sowmya
This change adds support to configure the DPTF policies based on the fw_config THERMAL_SOLUTION. BUG=b:238713292 TEST=Boot to OS and verify that dptf policies are set based on fw_config. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I0ffb9d7cc6c963add001a31ba23a6d6c351dd621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-30mb/google/brya/vell: Update amp SSIDShon Wang
The current subsystem ID used by the amps may end up getting used again for future products, therefore this CL updates the subsystem ID to 103C8C08, which was specifically generated for this amp. BUG=b:202484541 BRANCH=brya TEST='FW_NAME=vell emerge-brya coreboot' Change-Id: I399d8d99ead4fb6fdfa24c2a7a3e3d5e63603b8b Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-30mb/google/skyrim/var/winterhold: Update memory and RAMID tableEricKY Cheng
Update memory and RAMID table BRANCH=None BUG=b:243337816 TEST= emerge-coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Iec3c2098be86661249b1786a02f0768f9d8ad0ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/67106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-08-30util/spd_tools: Add AMD Mendocino (MDN) platformEricKY Cheng
This patch adds support for MDN platform to the spd_tools. This change replaces SBR with MDN. BUG=b:243337816 TEST=Able to generate SPD for LP5 DRAM part. Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: If099af36de8a64e96fbfde32eaf15990f4b330c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-30mb/google/skyrim/var/winterhold: Update Lp5x and Lp5 memory supportEricKY Cheng
Update K3KL8L80CM-MGCT, K3KL9L90CM-MGCT,H58G66AK6BX070 support BRANCH=None BUG=b:243337816 TEST= SPD add Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2c370fbd007c22b1f94074d9f16e5bc7c4e04848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>