diff options
| author | Bill XIE <persmule@hardenedlinux.org> | 2022-08-26 09:46:41 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-06 17:56:49 +0000 |
| commit | c547996c7cc11ace34b296324798591cc568cc96 (patch) | |
| tree | d56968ee1f051902652a96d99a268101fd1bc60d | |
| parent | 8dfb0f911176f82964d96be527d3e7a767815cec (diff) | |
mb/hp/z220_series: Add configs for integrated XHCI
Without these, all SuperSpeed ports are wired to EHCI #2.
"superspeed_capable_ports" and "xhci_switchable_ports" should fit both
CMT and SFF variants, while "xhci_overcurrent_mapping" should be
consistent with the first 4 elements of mainboard_usb_ports[].
With this commit, SuperSpeed devices plugged in SuperSpeed ports are
wired to the XHCI on my own Z220 SFF.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67089
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/hp/z220_series/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index ea8fad9320..bcacf7156e 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -33,6 +33,9 @@ chip northbridge/intel/sandybridge register "sata_interface_speed_support" = "0x3" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_switchable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x0000000f" device pci 14.0 on end # xHCI device pci 16.0 on end # Management Engine Interface 1 |