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2021-07-05mb/intel/adlrvp: Update the FIVR configurationsV Sowmya
This patch sets the optimized FIVR configuration for adlrvp cutomized based on the pnp measurements to achieve the better power savings in sleep states. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 states. * Update the supported voltage states. * Set the ICC max to 500mA for v1p05 and vnn. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-05soc/intel/alderlake: Add support to update the FIVR configsV Sowmya
This patch adds the supports to update the optimal FIVR configurations for external voltage rails via devicetree. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55702 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05mb/google/brya/brya0: Enable CrashlogTim Wawrzynczak
brya0 is a reference and development platform, therefore it would be helpful to have Crashlog enabled. Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-05mb/google/brya: Add HANG_DETECT host event to EC S0ix wake maskTim Wawrzynczak
The brya EC supports S0ix hang detection, but it was not enabled in coreboot as well, masking that event out of S0ix, therefore add it in to the EC S0ix wake mask. TEST=After EC prints "Warning: Detected sleep hang! Waking host up!", the host actually wakes up Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-05mb/google/dedede/var/cret: Disable SDCard controllerDtrain Hsu
Cret doesn't support SDCard. Disable SDCard contorller for Cret. BUG=b:191232222 TEST=Build and boot to check lspci Cq-Depend: chromium:2993724 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I889f0545883aa75813dd91dc3e6a4dcfc246687f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-05soc/intel/alderlake: Correct Bus and Device of Touch Host ControllerVarshit B Pandya
Correct Bus and Device for THC0 and THC1 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-04supermicro/x11: enable COMB via LPCAlexander Couzens
Allow to use the 2nd COM port of the AST2400 which can be also used via IPMI/serial-over-lan. Change-Id: I6f9c85b1f5428d3c3acf7a2f20296134c4611b1e Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-02util/cbfstool: Allow setting alignment for payloadRaul E Rangel
The -a flag was already implemented, it just wasn't exposed for the add-payload command. Setting the alignment of the payload will enable using the SPI DMA controller to read the payload on AMD devices. BUG=b:179699789 TEST=cbfstool foo.bin add-payload -a 64 ... Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/espi: Fix debug message log levelRaul E Rangel
BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see the message printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02drivers/intel/fsp2: Change FSPS returned message to INFORaul E Rangel
This message is not an error, but just informational. BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI readsRaul E Rangel
We are currently reading the uCode for each CPU. This is unnecessary since the uCode never changes. BUG=b:177909625 TEST=Boot guybrush and see "microcode: being updated to patch id" for each CPU. I no longer see CBFS access for each CPU. This drops device initialization time by 32 ms. Also boot Ezkinil and verify microcode was also updated. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-02soc/amd/cezanne: Enable SPI DMA supportRaul E Rangel
Start using the custom boot device. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ae7272677f563e8827ba154fe5177c8c01155c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/block/lpc: Add custom SPI DMA boot deviceRaul E Rangel
This is a copy of mmap_boot.c and mem_rdev_ro_ops. I split it up so it was easier to review. The next patches will add support for the SPI DMA controller. This will provide a minor speed up vs using mmap reads. It will also provide the facilities to perform asynchronous SPI loading. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id26e2a69601d0f31e256d0010008904a447c8e21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02arch/x86: Add X86_CUSTOM_BOOTMEDIARaul E Rangel
In order to disable X86_TOP4G_BOOTMEDIA_MAP it requires the definition to be overridden. This makes it a little less ergonomic to use. Instead introduce the inverse option that can be selected. I chose to leave X86_TOP4G_BOOTMEDIA_MAP since it keeps the Makefiles simple. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I65bbc118bde88687a7d7749c87acf1cbdc56a269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02cpu/qemu-x86: Increase heap sizeAngel Pons
On x86_64, the default heap size is too small when using 32 CPUs. Change-Id: Ib4f770a7a54d975d213b2456cc7d1ed9151cb6f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02src: Consolidate x86_64 support KconfigAngel Pons
Introduce `USE_EXP_X86_64_SUPPORT` in `src/arch/x86/Kconfig` and guard it with `HAVE_EXP_X86_64_SUPPORT`. Replace the per-CPU implementations of the same functionality with the newly-added Kconfig options. Update documentation and the config file for QEMU accordingly. Change-Id: I550216fd2a8323342d6b605306b0b95ffd5dcd1c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02mb/google/dedede/var/magolor: Enable G2 touchscreen for magmaTyler Wang
Add G2 touchscreen support for magma. BUG=b:189852808 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3e032bff7f3e97f54f3e544035e862058ea0dbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2021-07-02soc/intel/common/block/cse: Add ME EOP timestampsTim Wawrzynczak
BUG=b:191362590 TEST=on brya, cbmem -t: 942:before sending EOP to ME 2,628,446 (5,879) 943:after sending EOP to ME 2,631,177 (2,730) Change-Id: I0376610c5cbae7df1bf1a927b3bc99b1022de4cb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-02mb/google/volteer/variants/eldrid: Include SPD for MT40A512M16TB-062E:RMark Hsieh
Add SPD support to eldrid for DDR4 memory part MT40A512M16TB-062E:R. Eldrid should use DRAM_ID strap ID 0 (0000) on SKUs populated with MT40A512M16TB-062E:R DDR4 memory parts. BUG=b:192380070 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4d07727c9c41bf494fbef373abce0ac1fc65c316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55983 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02util/intelp2m: use import once for all included modulesMaxim Polyakov
There is no need to repeat "import" for each module in GoLang. Use this keyword only once in each file for code cleanliness. Change-Id: Ibb24fafd409b31b174946a39ca1f810d59b87e76 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55985 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02soc/intel/alderlake: Add USB TCSS enablementBernardo Perez Priego
In order to detect USB Type C device port as Super Speed, we need to set corresponding bit in UPD UsbTcPortEn. This patch will use device path to determine which port should be enabled. BUG=b:184324979 Test=Boot board, USB Type C must be functional and operate at Super Speed. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I7da63f21d51889a888699540f780cb26b480c26d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-02selfboot: Add support for selfload in romstageShelley Chen
Since bootmem is not available in romstage, calls to bootmem APIs need to be compile-time eliminated in order to avoid linker error: undefined reference to `bootmem_region_targets_type BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B cherry-picked on top of CB:49392 and verified successful compilation. Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55865 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01drivers/intel/gma: Move extended VBT just below opregionMaulik V Vaghela
Currently the flow for opregion init is as below: 1. Allocate memory for opregion first (cbmem_add(opregion)) 2. Check if VBT size > 6 KiB (this requires extended VBT support) 3. In case of extended VBT requirement, we allocate another chunk of memory which is equal to size of VBT (cbmem_add(extended_vbt)) 4. Pass physical address pointer to OS via RVDA We can optimize the above flow to allocate single chunk of memory by checking VBT size in earlier step. The new optimized flow for opregion init is as below: 1. Check if VBT size > 6 KiB (this requires extended VBT support) 2. In case of extended VBT requirement, total memory to be allocated is calculated as sizeof(opregion) + sizeof (extended_vbt) In case where VBT size is < 6 KiB, total memory requirement would be equal to sizeof(opregion) 3. Based on above calculation, allocate single chunk of memory based on total size. This will also be helpful for the case of virtualization where guest users don't have access to physical address and when it needs relative address of VBT compared to absolute address. In case of opregion 2.1 spec, we need to pass relative address of VBT from opregion base in RVDA. This optimization will help in meeting this requirement since relative address of extended VBT is easy to get. This change will ensure that it meets opregion specification requirement and will be compatible with future versions as well. BUG=b:190019970 BRANCH=None TEST=check the address of extended VBT region and address is coming correctly. Change-Id: Ic0e255df63145409096b0b9312c6c51c05f49931 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01cbfstool/cbfs-mkstage.c: Change signature of parse_elf_to_xip_stage()Arthur Heymans
The dereferced parameter is never updated so passing a copy would work too. Change-Id: Ie36f64f55d4fc7034780116c28aaed65aa304d5e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55792 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01mb/google/hatch/scout: update gpios and device treeJeff Chase
Scout-specific changes to puff reference following bring-up - copy baseline changes from genesis - update GPIOs - update PCIe ports for TPUs - remove LSPCON - enable eMMC - disable touch I2C - enable uart BUG=b:187078663 TEST=boot scout BRANCH=none Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/google/brya: Swap P-sensor IRQEric Lai
P-sensor is swap by the latest schematic. Thus, swap the IRQ for correct P-sensor. BUG=b:192331122,b:181555900 TEST=check P-sensor driver can be probed without error. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01soc/intel/alderlake: Enable energy efficiency turbo modeV Sowmya
This patch enables the energy efficiency turbo mode. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I2d76c948bdc9c208f5728e305b3034fcede6f4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55705 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01soc/intel: Refactor `xdci_can_enable()` functionAngel Pons
The same pattern appears on all `xdci_can_enable()` call sites. Move the logic inside the function and take the xDCI devfn as parameter. Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01drivers/intel/dptf: Add OEM variables supportSumeet R Pawnikar
This adds OEM variables feature under DPTF as per BWG doc #541817. Using this, platform vendors can expose an array of OEM-specific values as OEM variables to be used in determining DPTF policy. These are obtained via the ODVP method, and then simply exposed under sysfs. In addition, these gets updated when a notification is received or when the DPTF policy is changed by userspace. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01device: Clean up resource utility function signaturesKyösti Mälkki
Drop extern declarations from functions. Declare resource arguments as const. Change-Id: I7684cc7813bad805c39a762892636818279ac134 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55475 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01toolchain.inc: copy architecture specific CFLAGS to GCC_ADAFLAGSIru Cai
This fixes building with libgfxinit in x86_64 mode, which can generates unsupported R_X86_64_32S relocations without -mcmodel=large. Change-Id: If5162fae475f3e70c856d9664a8cfc6a89d82283 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55549 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01QEMU: Only call `pci_assign_irqs` with non-NULL devAngel Pons
Do not call `pci_assign_irqs` with a NULL device pointer. Change-Id: Ide9ae38dedd881ed673ba1838a1e29529b306937 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-01mb/emulation/qemu-i440fx: Tidy up PAM register writesAngel Pons
Tidy up the code that programs the PAM (Programmable Attribute Map) registers. Introduce the `D0F0_PAM` macro and use it to replace the magic `0x59` and `0x5a` values in the code. Adjust the range of the for-loop to work with the `D0F0_PAM` macro, and properly indent the loop's body. Change-Id: I9036425d726ffb69737ea6ed36c7a8f61d9d040a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-01mb/asus/p8x7x-series: Add P8C WS as a variant of P8X7X seriesBill XIE
Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-01mb/prodrive/hermes: Implement smbios_mainboard_versionPatrick Rudolph
Return the HSI version read from BMC in smbios_mainboard_version. Change-Id: If907d598c9e05d35f8898d294678f61d075f935a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-01mb/google/dedede: Create cappy2 variantSunway
Create the cappy2 variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192035460 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CAPPY2 Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/brya/variants/primus: Update mainboard properties for BB retimer ↵Casper Chang
upgrade This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:55348 BUG=b:191897776 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-01mb/google/dedede/var/drawcia: Add LTE modem support for drawperKevin Chiu
Add LTE modem to devicetree. Configure GPIO control for LTE modem by fw_config. Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:186393848 TEST=Build image and check with command modem status Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/dedede/var/kracko: Update LTE USB port configurationTony Huang
Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:178092096 BRANCH=dedede TEST=Build and boot to OS to check LTE by modem status Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01device/pci_device.c: Reuse `irq` variableAngel Pons
The `irq` variable has the same value as `pIntAtoD[line - 1]`. Change-Id: Iabf760adbc3014b32cfe6f908dc04c38b71bd980 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-01soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION configSubrata Banik
By enabling the flag alderlake platform will use hardware sha instruction instead of software implementation for sha256. This will speed up firmware verification especially on low-performance device. Change-Id: Ie8ab02360fdceafab257e9a301e6a89d3a22c3ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01vboot: add VBOOT_X86_SHA256_ACCELERATION configSubrata Banik
Add Kconfig option for VBOOT_X86_SHA256_ACCELERATION, which will use x86-sha extension for SHA256 instead of software implementation. TEST=Able to call vb2ex_hwcrypto_digest_init() and perform SHA using HW crypto engine. Change-Id: Idc8be8711c69f4ebc489cd37cc3749c0b257c610 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-01Update vboot submodule to upstream mainSubrata Banik
Updating from commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted to commit id ccc56f4: vboot: add x86 SHA256 ext support Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-01SMBIOS: Drop now-unnecessary unionsAngel Pons
Now that the refactoring is complete, the unions for the table header are no longer needed. Therefore, drop them. Change-Id: I4e170e84a12646386d3fd84ae973dd6c18f25809 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/emulation/qemu-i440fx/fw_cfg.c: Use `smbios_header`Angel Pons
Replace uses of `smbios_type0` with `smbios_header` for correctness. Change-Id: I2479984f5322f0fb474ff1707c1dd1f5885f30e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Introduce `smbios_full_table_len` functionAngel Pons
Introduce the `smbios_full_table_len` function to consolidate table length calculation. The case where the length of a table equals the length of the structure happens when a table has no strings. Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01arch/x86/smbios.c Move calculation next to usageAngel Pons
Change-Id: I949da86605e76b186ef2fdbfbc112b71544b694a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Introduce `smbios_carve_table` functionAngel Pons
Factor out some boilerplate code into a helper `smbios_carve_table` function, which zeroes out the table memory and fills in the header fields common to all tables. Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01SMBIOS: Introduce struct for SMBIOS table headerAngel Pons
All SMBIOS `type X` tables start with the same 4-byte header. Add a struct definition for it, and use it where applicable. The union is temporary and allows doing the necessary changes in smaller commits. Change-Id: Ibd9a80010f83fd7ebefc014b981d430f5723808c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/pcengines/apuX: Refactor to avoid dead assignmentAngel Pons
The initial value of `len` is never used. Declare and initialise all local variables in a single statement to avoid this problem. Change-Id: Ieb96758f4cd19d9d3f8fdc543e8ca17db06a2123 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Avoid `sizeof` on struct typeAngel Pons
Where applicable, use the size of the associated variable. Change-Id: Ibbac2a82893232a6f87182a6a965b84a599d633e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01arch/x86/smbios.c: Trim some `len` variablesAngel Pons
Reduce the scope or remove some `len` variables. This is done to ease replacing `sizeof` on struct types in a follow-up commit, by ensuring that all to-be-replaced appearances follow the variable declarations. Change-Id: Ied38fcaf87ef5b1e4f93076b4ba2898ad1f98a72 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01drivers/mrc_cache: Avoid `sizeof` on struct typeAngel Pons
Where applicable, use the size of the associated variable. Change-Id: Icf4f1c8fe9f54c44b041a65eb46d6ec9f9fd6367 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30commonlib: Add Intel-specific timestamps for before/after sending EOPTim Wawrzynczak
Change-Id: I11daebbfc44959f1e498ddac2ee7633e31a1a7d5 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2021-06-30soc/intel/jasperlake: Send End-of-Post message to CSETim Wawrzynczak
This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#619830. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I36fe448ff279ba054ad5e79e71c995dc915db21e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55633 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30soc/intel/tigerlake: Send End-of-Post message to CSETim Wawrzynczak
This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#612229 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iae6b2eac11c065749e57c5337d81ed20044fc903 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-30soc/intel/alderlake: Send End-of-Post message to CSETim Wawrzynczak
This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#627331. TEST=on brya, autotest firmware_CheckEOPState confirms ME is in post-boot state Change-Id: Iee8c29f81d5d04852ae3f16dc8a9ff0fa59f056a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-30soc/intel/common/block/cse: Add BWG error recovery to EOP failureTim Wawrzynczak
This patch adds functionality to attempt to allow booting in a secure configuration (albeit with potentially reduced functionality) when the CSE EOP message fails in any way. These steps come from the CSME BWG (13.5, 15.0, 16.), and tell the CSE to disable the MEI bus, which disables further communication from the host. This is followed by requesting the PMC to disable the MEI devices. If these steps are successful, then the boot firmware can continue to boot to the OS. Otherwise, die() is called, prefering not to boot over leaving the insecure MEI bus available. BUG=b:191362590 TEST=Set FSP UPD to disable sending EOP; called this function from a BS_PAYLOAD_LOAD, ON_ENTRY entry; observed that with just cse_mei_bus_disable() called, Linux can no longer communicate over MEI: [ 16.198759] mei_me 0000:00:16.0: wait hw ready failed [ 16.204488] mei_me 0000:00:16.0: hw_start failed ret = -62 [ 16.210804] mei_me 0000:00:16.0: H_RST is set = 0x80000031 [ 18.245909] mei_me 0000:00:16.0: wait hw ready failed [ 18.251601] mei_me 0000:00:16.0: hw_start failed ret = -62 [ 18.257785] mei_me 0000:00:16.0: reset: reached maximal consecutive.. [ 18.267622] mei_me 0000:00:16.0: reset failed ret = -19 [ 18.273580] mei_me 0000:00:16.0: link layer initialization failed. [ 18.280521] mei_me 0000:00:16.0: init hw failure. [ 18.285880] mei_me 0000:00:16.0: initialization failed. Calling both error recovery functions causes all of the slot 16 devices to fail to enumerate in the OS Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I06abf36a9d9d8a5f2afba6002dd5695dd2107db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55675 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30mb/google/brya/variants/gimble: init overridetree for gimbleMark Hsieh
init overridetree.cb based on the schematic carbine_adl-p_proto_20210618_proto final.pdf BUG=b:191213263 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I3f6875ef438b147436605629445d346a56896a87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30mb/google/brya/variants/primus: update gpiosCasper Chang
set GPP_C3 and GPP_C4 as NC since LAN function removal. BUG=b:190643562 Change-Id: I21214d0a2904ba4347fbbbc74237aca6db22c345 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55933 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30soc/intel/elkhartlake: Enable PCH GBELean Sheng Tan
Enable PCH GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Use EHL own GBE ACPI instead of common code version due to different B:D.F from the usual GBE 3. Add kconfig PMC_EPOC to use the PMC XTAL read function Due to EHL GBE comes with time sensitive networking (TSN) capability integrated, EHL FSP is using 'PchTsn' instead of the usual 'PchLan' naming convention across the board. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-30soc/intel/common: Refine pmc_get_xtal_freq functionLean Sheng Tan
1. Remove 'PCH_EPOC_XTAL_FREQ(__epoc)' macro since it only be used in 1 place. 2. Transform macro into more readable C code. 3. Add additional case check to make sure the returned value is defined in the 'pch_pmc_xtal' enum. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If57a99bf8e837a6eb8f225297399b1f5363cfa85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-30soc/intel/common: Move PMC EPOC related code to Intel common codeLean Sheng Tan
Move PMC EPOC related code to intel/common/block because it is generic for most Intel platforms and ADL, TGL & EHL use it. Add a kconfig 'PMC_EPOC' to guard this common EPOC code. The PMC EPOC register indicates which external crystal oscillator is connected to the PCH. This frequency is important for determining the IP clock of internal PCH devices. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib5fd3c4a648964678ee40ed0f60ca10fe7953f56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30ec/google: Use EC_HOST_EVENT_NONERob Barnes
google_chromeec_get_event returns 0 for no event. Return EC_HOST_EVENT_NONE=0 to improve readability. BUG=b:184074997 TEST=Build and boot guybrush without error Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30ec/google: Sync ec_commands.hRob Barnes
This change syncs the coreboot version of google ec_commands.h with the ec_commands.h from the google ec repository. This is a straight copy except for the the copyright header. BUG=b:184074997 TEST=Build and boot guybrush BRANCH=None Change-Id: I095c3316d720328cb7b8dd1b72ffc108208b14bd Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0Tao Xia
This change adds fine-tuned USB2 PHY parameters for storo. BUG=191089827 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I38dd8ad59b32f635e641765e0a1bd13651180d23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-30mb/google/dedede/var/storo: Enable Wifi SAR for storoTao Xia
BUG=b:190027970,b:178175837 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I7084f9b7be2b66adda2d9d5a83ce5dd9c31d01b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-30src: Move `select ARCH_X86` to platformsAngel Pons
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware, have platforms select `ARCH_X86` directly instead of through per-stage Kconfig options, effectively reversing the dependency order. Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-30soc/amd/common/fsp/dmi.c: Fix Type 17 DMI reportingNikolai Vyssotski
With two versions of *speed_mhz_to_reported_mts() we need to call the correct one based on the reported memory type. BUG=b:184124605 TEST="dmidecode --type 17" in OS on Guybrush Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I92e834097546e3ef7130830444a80f818bdea3d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55852 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30device/pci_device.c: Drop redundant guardAngel Pons
This guard is nested inside an identical guard already. Change-Id: I2b315ee6620865429097041035ad493ddcc51884 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-30mb/google/brya: Set GPP_B3 to APIC modeEric Lai
Set GPP_B3 to APIC mode to avoid PCI IRQ conflict. BUG=b:181555900 TEST=check dmesg there are no IRQ request errors like below. genirq: Flags mismatch irq 27. 00002008 (sx932x_event) vs. 00000080 (idma64.1) Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idf88fae9e244858445c45e66e26715cebe0c93ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30vc/mediatek/mt8195: Fix license headersRex-BC Chen
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If5e72b36242e1aff7ce2609ea6bdbaea53683bd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-29soc/intel/tigerlake: Enable support for common IRQ blockTim Wawrzynczak
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows tigerlake boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=b:171580862 TEST=on delbin, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 6 0 0 0 IO-APIC 2-edge timer 1: 0 35 0 0 IO-APIC 1-edge i8042 8: 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 601 0 0 IO-APIC 9-fasteoi acpi 14: 1 0 0 0 IO-APIC 14-fasteoi INT34C5:00 20: 0 0 0 516 IO-APIC 20-fasteoi idma64.6, ttyS0 28: 0 395 0 0 IO-APIC 28-fasteoi idma64.0, i2c_design 29: 0 0 1654 0 IO-APIC 29-fasteoi idma64.1, i2c_design 30: 0 0 0 0 IO-APIC 30-fasteoi idma64.2, i2c_design 31: 0 0 0 0 IO-APIC 31-fasteoi idma64.3, i2c_design 32: 0 0 0 0 IO-APIC 32-fasteoi idma64.4, i2c_design 33: 0 0 14469 0 IO-APIC 33-fasteoi idma64.5, i2c_design 35: 0 18494 0 0 IO-APIC 35-edge cr50_spi 36: 95705 0 0 0 IO-APIC 36-fasteoi idma64.7, pxa2xx-spi 37: 0 0 1978 0 IO-APIC 37-fasteoi idma64.8, pxa2xx-spi 51: 1865 0 0 0 IO-APIC 51-fasteoi ELAN9008:00 59: 0 0 422 0 IO-APIC 59-fasteoi ELAN0000:00 116: 0 0 0 23 IO-APIC 116-fasteoi chromeos-ec abbreviated _PRT dump: Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table If (PICM) Package () {0x0002FFFF, 0x00, 0x00, 0x10}, Package () {0x0004FFFF, 0x00, 0x00, 0x11}, Package () {0x0005FFFF, 0x00, 0x00, 0x12}, Package () {0x0006FFFF, 0x00, 0x00, 0x13}, Package () {0x0007FFFF, 0x00, 0x00, 0x14}, Package () {0x0007FFFF, 0x01, 0x00, 0x15}, Package () {0x0007FFFF, 0x02, 0x00, 0x16}, Package () {0x0007FFFF, 0x03, 0x00, 0x17}, Package () {0x000DFFFF, 0x00, 0x00, 0x10}, Package () {0x000DFFFF, 0x01, 0x00, 0x11}, Package () {0x000DFFFF, 0x02, 0x00, 0x12}, Package () {0x0010FFFF, 0x00, 0x00, 0x13}, Package () {0x0010FFFF, 0x01, 0x00, 0x14}, Package () {0x0011FFFF, 0x00, 0x00, 0x18}, Package () {0x0012FFFF, 0x00, 0x00, 0x19}, Package () {0x0012FFFF, 0x01, 0x00, 0x1A}, Package () {0x0013FFFF, 0x00, 0x00, 0x1B}, Package () {0x0014FFFF, 0x00, 0x00, 0x15}, Package () {0x0015FFFF, 0x00, 0x00, 0x1C}, Package () {0x0015FFFF, 0x01, 0x00, 0x1D}, Package () {0x0015FFFF, 0x02, 0x00, 0x1E}, Package () {0x0015FFFF, 0x03, 0x00, 0x1F}, Package () {0x0016FFFF, 0x00, 0x00, 0x16}, Package () {0x0016FFFF, 0x01, 0x00, 0x17}, Package () {0x0016FFFF, 0x02, 0x00, 0x10}, Package () {0x0016FFFF, 0x03, 0x00, 0x11}, Package () {0x0017FFFF, 0x00, 0x00, 0x12}, Package () {0x0019FFFF, 0x00, 0x00, 0x20}, Package () {0x0019FFFF, 0x01, 0x00, 0x21}, Package () {0x0019FFFF, 0x02, 0x00, 0x22}, Package () {0x001CFFFF, 0x00, 0x00, 0x10}, Package () {0x001CFFFF, 0x01, 0x00, 0x11}, Package () {0x001CFFFF, 0x02, 0x00, 0x12}, Package () {0x001CFFFF, 0x03, 0x00, 0x13}, Package () {0x001DFFFF, 0x00, 0x00, 0x10}, Package () {0x001DFFFF, 0x01, 0x00, 0x11}, Package () {0x001DFFFF, 0x02, 0x00, 0x12}, Package () {0x001DFFFF, 0x03, 0x00, 0x13}, Package () {0x001EFFFF, 0x00, 0x00, 0x14}, Package () {0x001EFFFF, 0x01, 0x00, 0x15}, Package () {0x001EFFFF, 0x02, 0x00, 0x24}, Package () {0x001EFFFF, 0x03, 0x00, 0x25}, Package () {0x001FFFFF, 0x01, 0x00, 0x17}, Package () {0x001FFFFF, 0x02, 0x00, 0x14}, Package () {0x001FFFFF, 0x03, 0x00, 0x15}, Package () {0x001FFFFF, 0x00, 0x00, 0x16}, Else Package () {0x0002FFFF, 0x00, 0x00, 0x0B}, Package () {0x0004FFFF, 0x00, 0x00, 0x0A}, Package () {0x0005FFFF, 0x00, 0x00, 0x0B}, Package () {0x0006FFFF, 0x00, 0x00, 0x0B}, Package () {0x0007FFFF, 0x00, 0x00, 0x0B}, Package () {0x0007FFFF, 0x01, 0x00, 0x0B}, Package () {0x0007FFFF, 0x02, 0x00, 0x0B}, Package () {0x0007FFFF, 0x03, 0x00, 0x0B}, Package () {0x000DFFFF, 0x00, 0x00, 0x0B}, Package () {0x000DFFFF, 0x01, 0x00, 0x0A}, Package () {0x000DFFFF, 0x02, 0x00, 0x0B}, Package () {0x0010FFFF, 0x00, 0x00, 0x0B}, Package () {0x0010FFFF, 0x01, 0x00, 0x0B}, Package () {0x0014FFFF, 0x00, 0x00, 0x0B}, Package () {0x0016FFFF, 0x00, 0x00, 0x0B}, Package () {0x0016FFFF, 0x01, 0x00, 0x0B}, Package () {0x0016FFFF, 0x02, 0x00, 0x0B}, Package () {0x0016FFFF, 0x03, 0x00, 0x0A}, Package () {0x0017FFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x01, 0x00, 0x0A}, Package () {0x001CFFFF, 0x02, 0x00, 0x0B}, Package () {0x001CFFFF, 0x03, 0x00, 0x0B}, Package () {0x001DFFFF, 0x00, 0x00, 0x0B}, Package () {0x001DFFFF, 0x01, 0x00, 0x0A}, Package () {0x001DFFFF, 0x02, 0x00, 0x0B}, Package () {0x001DFFFF, 0x03, 0x00, 0x0B}, Package () {0x001EFFFF, 0x00, 0x00, 0x0B}, Package () {0x001EFFFF, 0x01, 0x00, 0x0B}, Package () {0x001FFFFF, 0x01, 0x00, 0x0B}, Package () {0x001FFFFF, 0x02, 0x00, 0x0B}, Package () {0x001FFFFF, 0x03, 0x00, 0x0B}, Package () {0x001FFFFF, 0x00, 0x00, 0x0B}, Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ieb241f2b91af52a7e2d0efe997d35732882ac463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49409 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29soc/intel/alderlake: Enable support for common IRQ blockTim Wawrzynczak
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows ADL boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=b:176858827 TEST=brya0, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 36 0 0 0 0 0 0 0 IO-APIC 2-edge time 1: 0 0 9 0 0 0 0 0 IO-APIC 1-edge i804 8: 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 21705 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC 18: 0 0 0 0 0 0 0 0 IO-APIC 18-fasteoi inte 20: 0 0 0 0 0 0 0 394 IO-APIC 20-fasteoi idma 23: 2280 0 0 0 0 0 0 0 IO-APIC 23-fasteoi idma 26: 0 0 26 0 0 0 0 0 IO-APIC 26-fasteoi idma 27: 0 0 0 6 0 0 0 0 IO-APIC 27-fasteoi idma 28: 0 0 0 0 0 0 0 0 IO-APIC 28-fasteoi idma 29: 0 0 0 0 25784 0 0 0 IO-APIC 29-fasteoi idma 30: 0 0 0 0 0 0 0 0 IO-APIC 30-fasteoi idma 31: 0 0 0 0 0 0 226 0 IO-APIC 31-fasteoi idma 77: 0 0 0 0 0 2604 0 0 IO-APIC 77-edge cr50 100: 0 0 0 0 0 0 0 0 IO-APIC 100-fasteoi ELAN 103: 0 0 0 0 0 0 0 0 IO-APIC 103-fasteoi chro abbreviated _PRT dump: If (PICM) Package (){0x0002FFFF, 0, 0, 0x10}, Package (){0x0004FFFF, 0, 0, 0x11}, Package (){0x0005FFFF, 0, 0, 0x12}, Package (){0x0006FFFF, 0, 0, 0x13}, Package (){0x0006FFFF, 1, 0, 0x14}, Package (){0x0007FFFF, 0, 0, 0x15}, Package (){0x0007FFFF, 1, 0, 0x16}, Package (){0x0007FFFF, 2, 0, 0x17}, Package (){0x0007FFFF, 3, 0, 0x10}, Package (){0x000DFFFF, 0, 0, 0x11}, Package (){0x0012FFFF, 0, 0, 0x18}, Package (){0x0012FFFF, 1, 0, 0x19}, Package (){0x0014FFFF, 0, 0, 0x12}, Package (){0x0014FFFF, 1, 0, 0x13}, Package (){0x0015FFFF, 0, 0, 0x1A}, Package (){0x0015FFFF, 1, 0, 0x1B}, Package (){0x0015FFFF, 2, 0, 0x1C}, Package (){0x0015FFFF, 3, 0, 0x1D}, Package (){0x0016FFFF, 0, 0, 0x14}, Package (){0x0016FFFF, 1, 0, 0x15}, Package (){0x0016FFFF, 2, 0, 0x16}, Package (){0x0016FFFF, 3, 0, 0x17}, Package (){0x0017FFFF, 0, 0, 0x10}, Package (){0x0019FFFF, 0, 0, 0x1E}, Package (){0x0019FFFF, 1, 0, 0x1F}, Package (){0x0019FFFF, 2, 0, 0x20}, Package (){0x001CFFFF, 0, 0, 0x10}, Package (){0x001CFFFF, 1, 0, 0x11}, Package (){0x001CFFFF, 2, 0, 0x12}, Package (){0x001CFFFF, 3, 0, 0x13}, Package (){0x001DFFFF, 0, 0, 0x10}, Package (){0x001DFFFF, 1, 0, 0x11}, Package (){0x001DFFFF, 2, 0, 0x12}, Package (){0x001DFFFF, 3, 0, 0x13}, Package (){0x001EFFFF, 0, 0, 0x14}, Package (){0x001EFFFF, 1, 0, 0x15}, Package (){0x001EFFFF, 2, 0, 0x16}, Package (){0x001EFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 1, 0, 0x15}, Package (){0x001FFFFF, 2, 0, 0x16}, Package (){0x001FFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 0, 0, 0x14}, Else Package (){0x0002FFFF, 0, 0, 0x0B}, Package (){0x0004FFFF, 0, 0, 0x0A}, Package (){0x0005FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 0, 0, 0x0B}, Package (){0x0007FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 2, 0, 0x0B}, Package (){0x0007FFFF, 3, 0, 0x0B}, Package (){0x000DFFFF, 0, 0, 0x0A}, Package (){0x0014FFFF, 0, 0, 0x0B}, Package (){0x0014FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 0, 0, 0x0B}, Package (){0x0016FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 2, 0, 0x0B}, Package (){0x0016FFFF, 3, 0, 0x0B}, Package (){0x0017FFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 1, 0, 0x0A}, Package (){0x001CFFFF, 2, 0, 0x0B}, Package (){0x001CFFFF, 3, 0, 0x0B}, Package (){0x001DFFFF, 0, 0, 0x0B}, Package (){0x001DFFFF, 1, 0, 0x0A}, Package (){0x001DFFFF, 2, 0, 0x0B}, Package (){0x001DFFFF, 3, 0, 0x0B}, Package (){0x001EFFFF, 0, 0, 0x0B}, Package (){0x001EFFFF, 1, 0, 0x0B}, Package (){0x001EFFFF, 2, 0, 0x0B}, Package (){0x001EFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 1, 0, 0x0B}, Package (){0x001FFFFF, 2, 0, 0x0B}, Package (){0x001FFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 0, 0, 0x0B}, dmesg shows no GSI or PCI errors, TPM & touchpad IRQs still work Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1e7a708183ac4170b28da9565137fa2f5088a7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/54683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29soc/intel/cannonlake: Use new IRQ moduleTim Wawrzynczak
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows cannonlake boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. Also prodrive/hermes (intel/cannonlake) was the only user of uart_acpi_write_irq(), therefore use the allocated IRQ instead of the fixed IRQ number in that function to preserve behavior. BUG=b:130217151 TEST=on dratini, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 11 0 0 0 IO-APIC 2-edge timer 1: 0 661 0 0 IO-APIC 1-edge i8042 8: 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 874 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 1 0 IO-APIC 14-fasteoi INT34BB:00 17: 0 10633 0 0 IO-APIC 17-fasteoi mmc1 19: 0 0 0 0 IO-APIC 19-fasteoi mmc0 22: 0 0 0 0 IO-APIC 22-fasteoi i801_smbus 26: 153738 0 0 0 IO-APIC 26-fasteoi idma64.0, i2c_designwar 27: 0 8 0 0 IO-APIC 27-fasteoi idma64.1, i2c_designwar 30: 0 0 227 0 IO-APIC 30-fasteoi i2c_designware.2 33: 0 0 0 0 IO-APIC 33-fasteoi idma64.3 35: 43107 0 0 0 IO-APIC 35-fasteoi idma64.4, pxa2xx-spi.4 36: 0 0 2039 0 IO-APIC 36-fasteoi idma64.5, pxa2xx-spi.5 45: 0 0 9451 0 IO-APIC 45-edge ELAN0000:00 85: 0 0 0 0 IO-APIC 85-fasteoi chromeos-ec 93: 0 7741 0 0 IO-APIC 93-edge cr50_spi abbreviated _PRT dump: If (PICM) Package () {0x0001FFFF, 0x00, 0x00, 0x10}, Package () {0x0001FFFF, 0x01, 0x00, 0x11}, Package () {0x0001FFFF, 0x02, 0x00, 0x12}, Package () {0x0002FFFF, 0x00, 0x00, 0x13}, Package () {0x0004FFFF, 0x00, 0x00, 0x14}, Package () {0x0005FFFF, 0x00, 0x00, 0x15}, Package () {0x0008FFFF, 0x00, 0x00, 0x16}, Package () {0x0012FFFF, 0x01, 0x00, 0x17}, Package () {0x0012FFFF, 0x02, 0x00, 0x10}, Package () {0x0012FFFF, 0x00, 0x00, 0x18}, Package () {0x0013FFFF, 0x00, 0x00, 0x19}, Package () {0x0014FFFF, 0x00, 0x00, 0x11} Package () {0x0014FFFF, 0x01, 0x00, 0x12}, Package () {0x0014FFFF, 0x02, 0x00, 0x13}, Package () {0x0014FFFF, 0x03, 0x00, 0x14}, Package () {0x0015FFFF, 0x00, 0x00, 0x1A}, Package () {0x0015FFFF, 0x01, 0x00, 0x1B}, Package () {0x0015FFFF, 0x02, 0x00, 0x1C}, Package () {0x0015FFFF, 0x03, 0x00, 0x1D}, Package () {0x0016FFFF, 0x00, 0x00, 0x15}, Package () {0x0016FFFF, 0x01, 0x00, 0x16}, Package () {0x0016FFFF, 0x02, 0x00, 0x17}, Package () {0x0016FFFF, 0x03, 0x00, 0x10}, Package () {0x0017FFFF, 0x00, 0x00, 0x11}, Package () {0x0019FFFF, 0x00, 0x00, 0x1E}, Package () {0x0019FFFF, 0x01, 0x00, 0x1F}, Package () {0x0019FFFF, 0x02, 0x00, 0x20}, Package () {0x001AFFFF, 0x00, 0x00, 0x12}, Package () {0x001CFFFF, 0x00, 0x00, 0x10}, Package () {0x001CFFFF, 0x01, 0x00, 0x11}, Package () {0x001CFFFF, 0x02, 0x00, 0x12}, Package () {0x001CFFFF, 0x03, 0x00, 0x13}, Package () {0x001DFFFF, 0x00, 0x00, 0x10}, Package () {0x001DFFFF, 0x01, 0x00, 0x11}, Package () {0x001DFFFF, 0x02, 0x00, 0x12}, Package () {0x001DFFFF, 0x03, 0x00, 0x13}, Package () {0x001EFFFF, 0x00, 0x00, 0x21}, Package () {0x001EFFFF, 0x01, 0x00, 0x22}, Package () {0x001EFFFF, 0x02, 0x00, 0x23}, Package () {0x001EFFFF, 0x03, 0x00, 0x24}, Package () {0x001FFFFF, 0x01, 0x00, 0x15}, Package () {0x001FFFFF, 0x02, 0x00, 0x16}, Package () {0x001FFFFF, 0x03, 0x00, 0x17}, Package () {0x001FFFFF, 0x00, 0x00, 0x14}, Else Package () {0x0001FFFF, 0x00, 0x00, 0x0B}, Package () {0x0001FFFF, 0x01, 0x00, 0x0A}, Package () {0x0001FFFF, 0x02, 0x00, 0x0B}, Package () {0x0002FFFF, 0x00, 0x00, 0x0B}, Package () {0x0004FFFF, 0x00, 0x00, 0x0B}, Package () {0x0005FFFF, 0x00, 0x00, 0x0B}, Package () {0x0008FFFF, 0x00, 0x00, 0x0B}, Package () {0x0012FFFF, 0x01, 0x00, 0x0B}, Package () {0x0012FFFF, 0x02, 0x00, 0x0B}, Package () {0x0014FFFF, 0x00, 0x00, 0x0A}, Package () {0x0014FFFF, 0x01, 0x00, 0x0B}, Package () {0x0014FFFF, 0x02, 0x00, 0x0B}, Package () {0x0014FFFF, 0x03, 0x00, 0x0B}, Package () {0x0016FFFF, 0x00, 0x00, 0x0B}, Package () {0x0016FFFF, 0x01, 0x00, 0x0B}, Package () {0x0016FFFF, 0x02, 0x00, 0x0B}, Package () {0x0016FFFF, 0x03, 0x00, 0x0B}, Package () {0x0017FFFF, 0x00, 0x00, 0x0A}, Package () {0x001AFFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x01, 0x00, 0x0A}, Package () {0x001CFFFF, 0x02, 0x00, 0x0B}, Package () {0x001CFFFF, 0x03, 0x00, 0x0B}, Package () {0x001DFFFF, 0x00, 0x00, 0x0B}, Package () {0x001DFFFF, 0x01, 0x00, 0x0A}, Package () {0x001DFFFF, 0x02, 0x00, 0x0B}, Package () {0x001DFFFF, 0x03, 0x00, 0x0B}, Package () {0x001FFFFF, 0x01, 0x00, 0x0B}, Package () {0x001FFFFF, 0x02, 0x00, 0x0B}, Package () {0x001FFFFF, 0x03, 0x00, 0x0B}, Package () {0x001FFFFF, 0x00, 0x00, 0x0B}, Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I914ac65470635f351d6311dc9b65e8e4d8d8ecfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55968 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29soc/intel/cannonlake: Add some missing DEVFN macrosTim Wawrzynczak
BUG=b:130217151 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If535ad0bdd46d3315493155e64968d305aa34799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55967 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29soc/intel/common/irq: Add function to return IRQ for PCI devfnTim Wawrzynczak
The IRQ for a single device may be required elsewhere, therefore provide get_pci_devfn_irq. BUG=b:130217151, b:171580862, b:176858827 Change-Id: Ibebd821767a2698c9e60b09eeeff3bb596359728 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55826 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29soc/intel/common/irq: Internally cache PCI IRQ resultsTim Wawrzynczak
The results of the PCI IRQ assignments are used in several places, so it makes for a nicer API to cache the results and provide simpler functions for the SoCs to call. BUG=b:130217151, b:171580862, b:176858827 Change-Id: Id79eae3f2360cd64f66e7f53e1d78a23cfe5e9df Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55825 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29soc/intel/common/irq: Add function to program north PCI IRQsTim Wawrzynczak
Because the FSP interface for PCI IRQs only includes the PCH devices, this function is the complement to that, taking the list of irq entries, and programming the PCI_INTERRUPT_LINE registers. BUG=b:130217151, b:171580862, b:176858827 TEST=boot brya with patch train, verify with `lspci -vvv` that for all the north PCI devices, their IRQ was either the one programmed by this function, or an MSI was used. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I81cf7b25f115e41deb25767669b5466b5712b177 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55817 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29soc/intel/common/block/irq: Add support for intel_write_pci0_PRTTim Wawrzynczak
Add a new function to fill out the data structures necessary to generate a _PRT table. BUG=b:130217151, b:171580862, b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51159 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29soc/intel/common: Add new IRQ moduleTim Wawrzynczak
The Intel FSP provides a default set of IO-APIC IRQs for PCI devices, if the DevIntConfigPtr UPD is not filled in. However, the FSP has a list of rules that the input IRQ table must conform to: 1) One entry per slot/function 2) Functions using PIRQs must use IOxAPIC IRQs 16-23 3) Single-function devices must use INTA 4) Each slot must have consistent INTx<->PIRQy mappings 5) Some functions have special interrupt pin requirements 6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIN) 7) Some functions require a unique IRQ number 8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes its IRQ through IO-APIC. Since the FSP has no visibility into the actual GPIOs used on the board when GpioOverride is selected, IRQ conflicts can occur between PCI devices and GPIOs. This patch gives SoC code the ability to generate a table of PCI IRQs that will meet the BWG/FSP rules and also not conflict with GPIO IRQs. BUG=b:130217151, b:171580862, b:176858827 TEST=Boot with patch series on volteer, verify IO-APIC IRQs in `/proc/interrupts` match what is expected. No `GSI INT` or `could not derive routing` messages seen in `dmesg` output. Verified TPM, touchpad, touchscreen IRQs all function as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49408 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29southbridge/intel/common: Move invalid PIRQ value to 0Tim Wawrzynczak
This makes structs that contain an `enum pirq` field that is default-initialized have the value PIRQ_INVALID Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idb4c7d79de13de0e4b187a42e8bdb27e25e61cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55281 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29mb/google/guybrush: Initialize WWAN for USB if requestedMartin Roth
To set the Fibocom 850-GL module to USB mode, it needs to be disabled when PCIe training happens, or it will automatically switch to PCIe mode. This patch makes sure it's shut down when training happens in FSP-M. It will be brought up in ramstage and will be available for USB enumeration later. BUG=b:187316460 TEST=Run lsusb from the OS and see that the Fibocom module is present on USB. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/guybrush: Update romstage power-on timings for PCIeMartin Roth
This configures the romstage portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe devices out of reset, both need to be brought hign. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29mb/google/guybrush: Update bootblock power-on timings for PCIeMartin Roth
This configures the bootblock portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. Setting the PCIE Reset happens in coreboot instead of in the FSP. The Aux reset lines are anded with the PCIe RST line, so both have to be brought up together. On v1 of guybrush, the PCIe reset line also resets EC communication, so it must be brought up immediately on that version. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29Kconfig: Escape variablesPatrick Georgi
New kconfig parsers interpret $(var) themselves, leading to empty fields. Old kconfig understands \$(var), so use that. Change-Id: I927fc9dc7a66211bfe51d4324cf7c51b555ea3a8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55912 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29mb/google/herobrine: Add Senor and Piglin variantsShelley Chen
Add configs for Herobrine variants. Also enable ec sw sync as this should not be disabled by default. BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B ./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-29mb/google/guybrush: provide full range backlight settings to kernelPratik Vishwakarma
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:190443612 Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835 Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/brya0: Enable MIPI UFCVarshit B Pandya
1. Add 2 port 2 endpoint 2. Add support for OVTI5675 3. Guard entries in override device tree by FW_CONFIG MIPI UFC is on I2C2 This configuration is as per P2 schematics BUG=b:190674542 TEST=Build and Boot on Brya Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-28mb/google/guybrush: Configure eSPI requirements before setting it upMartin Roth
When initializing eSPI early, guybrush has requirements to configure the bus properly. Those are normally run in bootblock_mainboard_early_init, but when setting up eSPI early, those have not run yet. BUG=192100564 TEST=Build along with previous patch, eSPI works on guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28soc/amd/cezanne: Add call to mb to configure eSPI requirementsMartin Roth
When initializing espi early, there may be mainboard requirements to configure the bus properly. This allows the mainboard to do that. BUG=192100564 TEST=Build along with next patch, eSPI works on guybrush Change-Id: Icc02877a09b8f8ed20fd1b04f3cee0509f1a85c5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-28mb/google/volteer/var/volet: add G2 touch supportSheng-Liang Pan
Enable G2 touchscreen support for Volet. BUG=b:185097280 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I907356448b5d5cbf3974717654ea09cd995962f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55835 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/dedede/var/blipper: Update devicetree and gpio settingZanxi Chen
To reduce power load, set unused GPIOs to NC and close unused interface in devicetree. GPIOs and interfaces are as below: GPIO: GPP_C18/C19/D12/D14/D15/D19/D20/D21/E00/E02/H06/H07 Interface: I2C1/I2C3/I2C5 USB: port2_3/2_4/2_6 BUG=b:185044041 BRANCH=dedede TEST=Built bios and test, it reduces power load without affecting device function. Change-Id: Ib5999f0e129bf3e660fe293eda7af3e8e1426151 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.com>
2021-06-28mb/google/brya0: Add FW_CONFIG for UFCVarshit B Pandya
UFC on brya can be USB or MIPI Add FW_CONFIG bit for this option Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I2f1492d7c769aba8da80763124dda474b32cfbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-28mb/google/brya: Update mainboard properties for BB retimer upgradeMaulik V Vaghela
This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:54292 BUG=b:186521258 TEST=Updated BB retimer FW from 3.4 to 3.5 without any device connected. Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-28mb/google/dedede/var/sasukette: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I4dbe3947779395903d7999627948d3e97d6cc985 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-28src/device/dram: Add terminating new lines to printk stringsNikolai Vyssotski
BUG=b:184124605 TEST=check serial log Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I521a2541e23d047e255b0cc8068ad63dfaf70bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-28mb/google/dedede/var/cret: Add ssfc codec cs42l42 supportDtrain Hsu
Add cs42l42 codec support in cret. BUG=b:188623237, b:189073353 TEST=Build and boot to check functional with cs42l42 EV board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55091 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/intel/adlrvp_m: Enable TCSS USB ports device pathBernardo Perez Priego
This provide a more consistent mechanism to enable corresponding USB TCSS port. BUG=b:182960979 TEST=Boot device, Type C port should operate correctly. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>