diff options
Diffstat (limited to 'src')
6 files changed, 137 insertions, 171 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 26feab441c..09da24cc2a 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,12 +34,16 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" - register "SataPortsDevSlp[2]" = "0" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + register "SataPortsDevSlp" = "{ + [0] = 0, + [1] = 0, + [2] = 0, + }" register "SataSpeedLimit" = "2" register "DspEnable" = "1" register "IoBufferOwnership" = "0" @@ -129,20 +133,23 @@ chip soc/intel/skylake register "PcieRpClkSrcNumber[10]" = "3" register "PcieRpClkSrcNumber[11]" = "3" + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */ + [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */ + }" - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + }" # PL2 override 25W register "power_limits_config" = "{ diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 9e6d4fbd81..f88c99d0c7 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -23,9 +23,11 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "0" - register "SataPortsEnable[1]" = "0" - register "SataPortsEnable[2]" = "0" + register "SataPortsEnable" = "{ + [0] = 0, + [1] = 0, + [2] = 0, + }" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" @@ -124,23 +126,23 @@ chip soc/intel/skylake register "PcieRpHotPlug[4]" = "1" - # USB - register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) - - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Camera - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # Keyboard - register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)" # Touchscreen - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC1), /* Type-A Port (right) */ + [1] = USB2_PORT_MID(OC1), /* Type-A Port (left) */ + [2] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [3] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [4] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [5] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [6] = USB2_PORT_FLEX(OC2), /* Camera */ + [7] = USB2_PORT_FLEX(OC2), /* Keyboard */ + [8] = USB2_PORT_FLEX(OC2), /* Touchscreen */ + }" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (left) */ + [1] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (right) */ + [5] = USB3_PORT_DEFAULT(OC1), /* TODO Unknown. Maybe USBC? */ + }" # PL1 override 25W # PL2 override 44W diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 35825f8630..4d54afe828 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -15,41 +15,30 @@ chip soc/intel/skylake # This board has an IGD with no output. register "PrimaryDisplay" = "Display_Auto" - # USB configuration - # USB2/3 - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), /* USB 2 */ + [1] = USB2_PORT_MID(OC0), /* USB 3 */ + [2] = USB2_PORT_MID(OC1), /* USB 4 */ + [3] = USB2_PORT_MID(OC1), /* USB 5 */ + [4] = USB2_PORT_MID(OC2), /* USB 0 */ + [5] = USB2_PORT_MID(OC2), /* USB 1 */ + [8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ + [9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */ + [10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ + [11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ + [12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */ + [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ + [14] = USB2_PORT_MID(OC0), /* Unknown */ + [15] = USB2_PORT_MID(OC0), /* Unknown */ + }" - # ? - register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" - - # USB4/5 - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" - - # USB0/1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - - # USB9/10 (USB3.0) - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" - - # USB6/7 (USB3.0) - register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" - - # USB8 (USB3.0) - register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" - - # IPMI USB HUB - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */ + [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ + [2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ + [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ + [4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */ + }" device domain 0 on device pci 01.0 on diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index d7f5df8c8b..56b8f9ce7b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -14,41 +14,30 @@ chip soc/intel/skylake # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" - # USB configuration - # USB2/3 - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), /* USB 2 */ + [1] = USB2_PORT_MID(OC0), /* USB 3 */ + [2] = USB2_PORT_MID(OC1), /* USB 4 */ + [3] = USB2_PORT_MID(OC1), /* USB 5 */ + [4] = USB2_PORT_MID(OC2), /* USB 0 */ + [5] = USB2_PORT_MID(OC2), /* USB 1 */ + [8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ + [9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */ + [10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ + [11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ + [12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */ + [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ + [14] = USB2_PORT_MID(OC0), /* Unknown */ + [15] = USB2_PORT_MID(OC0), /* Unknown */ + }" - # ? - register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" - - # USB4/5 - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" - - # USB0/1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - - # USB9/10 (USB3.0) - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" - - # USB6/7 (USB3.0) - register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" - - # USB8 (USB3.0) - register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" - - # IPMI USB HUB - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */ + [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ + [2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ + [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ + [4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */ + }" device domain 0 on device pci 01.0 on end # unused diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 5845607142..66206a6100 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -11,37 +11,28 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # USB configuration - # USB0/1 - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ + [1] = USB2_PORT_MID(OC3), /* USB 8 (3.0) */ + [2] = USB2_PORT_MID(OC1), /* USB 3 */ + [3] = USB2_PORT_MID(OC1), /* USB 2 */ + [4] = USB2_PORT_MID(OC2), /* USB 1 */ + [5] = USB2_PORT_MID(OC2), /* USB 0 */ + [6] = USB2_PORT_MID(OC0), /* USB 5 */ + [7] = USB2_PORT_MID(OC0), /* USB 4 */ + [8] = USB2_PORT_MID(OC_SKIP), /* IPMI USB HUB */ + [9] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */ + [10] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ + [11] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ + }" - # USB2/3 - register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" - - # USB4/5 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - - # USB6/7 (USB3.0) - register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" - register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" - - # USB8/9 (USB3.0) - register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" - register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - - # USB10 (USB3.0) - register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" - - # IPMI USB HUB - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ + [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ + [2] = USB3_PORT_DEFAULT(OC5), /* USB 10 */ + [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ + [4] = USB3_PORT_DEFAULT(OC3), /* USB 8 */ + }" device domain 0 on subsystemid 0x15d9 0x0896 inherit diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index 6984b834ed..c5c2778a20 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -15,43 +15,31 @@ chip soc/intel/skylake # This board has an IGD with no output. register "PrimaryDisplay" = "Display_Auto" - # USB configuration # NB: Overcurrent OCx values untested - # USB2/3 - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC3), /* USB 6 (3.0) */ + [1] = USB2_PORT_MID(OC3), /* USB 7 (3.0) */ + [2] = USB2_PORT_MID(OC2), /* USB 0 */ + [3] = USB2_PORT_MID(OC2), /* USB 1 */ + [4] = USB2_PORT_MID(OC1), /* USB 4 */ + [5] = USB2_PORT_MID(OC1), /* USB 5 */ + [8] = USB2_PORT_MID(OC0), /* USB 2 */ + [9] = USB2_PORT_MID(OC0), /* USB 3 */ + [10] = USB2_PORT_MID(OC5), /* USB 9 (3.0) */ + [11] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */ + [12] = USB2_PORT_MID(OC4), /* USB 8 (3.0) */ + [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ + [14] = USB2_PORT_MID(OC0), /* Unknown */ + [15] = USB2_PORT_MID(OC0), /* Unknown */ + }" - # ? - register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" - - # USB4/5 - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" - - # USB0/1 - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" - - # USB6/7 (USB3.0) - register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" - - # USB8 (USB3.0) - register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" - - # USB9/10 (USB3.0) - register "usb2_ports[10]" = "USB2_PORT_MID(OC5)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC5)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)" - - - # IPMI USB HUB - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC3), /* USB 6 */ + [1] = USB3_PORT_DEFAULT(OC3), /* USB 7 */ + [2] = USB3_PORT_DEFAULT(OC4), /* USB 8 */ + [3] = USB3_PORT_DEFAULT(OC5), /* USB 9 */ + [4] = USB3_PORT_DEFAULT(OC5), /* USB 10 */ + }" device domain 0 on device pci 01.0 on |