diff options
Diffstat (limited to 'src/mainboard/libretrend/lt1000/devicetree.cb')
| -rw-r--r-- | src/mainboard/libretrend/lt1000/devicetree.cb | 45 |
1 files changed, 26 insertions, 19 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 26feab441c..09da24cc2a 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,12 +34,16 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" - register "SataPortsDevSlp[2]" = "0" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + register "SataPortsDevSlp" = "{ + [0] = 0, + [1] = 0, + [2] = 0, + }" register "SataSpeedLimit" = "2" register "DspEnable" = "1" register "IoBufferOwnership" = "0" @@ -129,20 +133,23 @@ chip soc/intel/skylake register "PcieRpClkSrcNumber[10]" = "3" register "PcieRpClkSrcNumber[11]" = "3" + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */ + [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */ + }" - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + }" # PL2 override 25W register "power_limits_config" = "{ |