diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f10')
7 files changed, 15 insertions, 15 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c index 1dbe4406f8..3a3be35235 100644 --- a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c @@ -120,7 +120,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -151,7 +151,7 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData &= 0xFFFFFFFFFFF7FFFFull; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c index 10f4f5c4f1..87dda2a575 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c @@ -208,7 +208,7 @@ AllocateExecutionCache ( GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, StdHeader); - // Setup MTTRs for region 0 to region 2 + // Setup MTRRs for region 0 to region 2 VariableMttrBase = AMD_MTRR_VARIABLE_BASE6; for (i = 0; i < 3; i++) { // Exit if no more cache available @@ -265,7 +265,7 @@ AllocateExecutionCache ( if (StartAddr < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region if ((StartAddr + ExeCacheSize) > 0xFFFFF) { ExeCacheSize = 0xFFFFF - StartAddr; AgesaStatus = AGESA_WARNING; @@ -276,7 +276,7 @@ AllocateExecutionCache ( i, StartAddr, ExeCacheSize, 0, StdHeader); } - // Find start and end of MTTR + // Find start and end of MTRR StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((StartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + (((StartAddr + ExeCacheSize) >> 15) & 0x7); @@ -290,14 +290,14 @@ AllocateExecutionCache ( } } - // Setup MTTRs + // Setup MTRRs MsrData = WP_IO; for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) { LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader); } } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region if (VariableMttrBase > AMD_MTRR_VARIABLE_BASE7) { AgesaStatus = AGESA_ERROR; AgesaInfo = AGESA_THREE_CACHE_REGIONS_ABOVE_1MB; @@ -373,7 +373,7 @@ AllocateExecutionCache ( } } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData &= 0xFFFFFFFFFFF7FFFFull; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm index 0b796c8510..e92c94517f 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm @@ -147,7 +147,7 @@ EFLoop: .endw .endif - ; restore variable MTTR6 and MTTR7 to default states + ; restore variable MTRR6 and MTRR7 to default states mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6 xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7 xor edx, edx diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c index 2421bb9570..789a6bd856 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c @@ -156,7 +156,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); } - // restore variable MTTR6 and MTTR7 to default states + // restore variable MTRR6 and MTRR7 to default states for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared __writemsr (msrno, 0); diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c index b5be972444..aa79b16820 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c @@ -153,7 +153,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f10/cpcarmac.inc b/src/vendorcode/amd/agesa/f10/cpcarmac.inc index f7119d1cf3..e893d1ef8b 100644 --- a/src/vendorcode/amd/agesa/f10/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f10/cpcarmac.inc @@ -187,7 +187,7 @@ SetupDramMap: inc cl .endw - ; setup MTTR for stacks + ; setup MTRR for stacks mov ebx, WB_DRAM_TYPE .if (di == 0) ;core 0 .if (si > 3) ; node 0 to 3 located at 40000h, node 4 to 7 located at 50000h @@ -198,7 +198,7 @@ SetupDramMap: or edx, ebx _WRMSR .else ;core 1 to core 7 start at 60000h - .if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTTR + .if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTRR shl ebx, 16 .if (si > 1) shl ebx, 8 @@ -207,7 +207,7 @@ SetupDramMap: _RDMSR or edx, ebx _WRMSR - .else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTTR + .else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTRR mov ecx, AMD_MTRR_FIX16k_80000 _RDMSR .if (si < 6) ; node 4 and node 5 diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index 2f0e0836b0..b89834fc21 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -1353,7 +1353,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. |