diff options
Diffstat (limited to 'src/superio/ite/common')
| -rw-r--r-- | src/superio/ite/common/early_serial.c | 21 | ||||
| -rw-r--r-- | src/superio/ite/common/ite.h | 1 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 5ff403f497..552f1104ba 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -15,6 +15,7 @@ #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ #define ITE_CONFIG_REG_WDT_TIMEOUT_LSB 0x73 /* watchdog timeout (LSB) */ #define ITE_CONFIG_REG_WDT_TIMEOUT_MSB 0x74 /* watchdog timeout (MSB) */ +#define ITE_CONFIG_REG_APC_PME_CTL2 0xf4 /* APC_PME Control 2 */ /* Helper procedure */ static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) @@ -136,3 +137,23 @@ void ite_kill_watchdog(pnp_devfn_t dev) ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_MSB, 0x00); pnp_exit_conf_state(dev); } + +/* + * Set AC resume to be up to the Southbridge + * pass EC_DEV + */ +void ite_ac_resume_southbridge(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL2); + /* + * Set both + * 6: Gate Extra PWRON# Pulse + * 5: PSON# state when 3VSB switched to on + */ + tmp |= 0x60; + pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL2, tmp); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 3e9b50289a..19ade4b9b6 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -17,6 +17,7 @@ void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); void ite_enable_3vsbsw(pnp_devfn_t dev); void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev); +void ite_ac_resume_southbridge(pnp_devfn_t dev); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev); |