diff options
Diffstat (limited to 'src/southbridge/intel')
34 files changed, 30 insertions, 82 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 3b05a3e678..06ac5c6455 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -11,6 +11,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 687fc97d4c..a591aabea0 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,4 +38,6 @@ else romstage-y += early_me_mrc.c early_usb_mrc.c endif +CPPFLAGS_common += -I$(src)/southbridge/intel/bd82x6x/include + endif diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h index 949467b61c..949467b61c 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 73946d29bc..c2e7a86f09 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -18,13 +18,13 @@ #include <string.h> #include "chip.h" #include "pch.h" -#include "nvs.h" #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/spi.h> +#include <soc/nvs.h> #define NMI_OFF 0 @@ -641,16 +641,6 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - -void *gnvs_chromeos_ptr(struct global_nvs *gnvs) -{ - return &gnvs->chromeos; -} - void soc_fill_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 3b37b06f83..bef98fae10 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -9,6 +9,7 @@ #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <soc/nvs.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> #include <cpu/intel/model_206ax/model_206ax.h> @@ -16,7 +17,6 @@ #include <southbridge/intel/common/finalize.h> #include "pch.h" -#include "nvs.h" int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 433555d8c4..7507cd5d5d 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/device.h> #include "i82371eb.h" @@ -45,8 +44,3 @@ unsigned long acpi_fill_mcfg(unsigned long current) /* chipset doesn't have mmconfig */ return current; } - -size_t gnvs_size_of_array(void) -{ - return 0; -} diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index 66aa3f1ba9..84ea73ad9c 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <version.h> /* FIXME: This needs to go into a separate .h file @@ -80,8 +79,3 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe0_blk.addrl = pmbase + 0x28; fadt->x_gpe0_blk.addrh = 0x0; } - -size_t gnvs_size_of_array(void) -{ - return 0; -} diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2cd56e95ff..c8807935a2 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801GX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select IOAPIC select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 11a9c0007d..95402a1dfc 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -25,4 +25,6 @@ smm-y += smihandler.c romstage-y += early_init.c romstage-y += early_cir.c +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801gx/include + endif diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h index b23b85bec2..b23b85bec2 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 74cadc8df4..4b7898c75e 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -21,10 +21,10 @@ #include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/spi.h> +#include <soc/nvs.h> #include "chip.h" #include "i82801gx.h" -#include "nvs.h" #define NMI_OFF 0 @@ -464,11 +464,6 @@ static void lpc_final(struct device *dev) outb(POST_OS_BOOT, 0x80); } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - void soc_fill_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 03480a7903..67a8cf8cf4 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> +#include <soc/nvs.h> #include <southbridge/intel/common/pmutil.h> #include "i82801gx.h" @@ -15,8 +16,6 @@ #define G_SMRANE (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#include "nvs.h" - /* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index be640db0c3..3ee2943090 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select HAVE_SMI_HANDLER if !NO_SMM select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 516a344e62..8eabd49300 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -29,4 +29,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S endif +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include + endif diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h index 83dd7e508d..83dd7e508d 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 0b58e67425..b84b458027 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -12,13 +12,11 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <string.h> #include "chip.h" #include "i82801ix.h" -#include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/acpi_pirq_gen.h> @@ -452,17 +450,6 @@ static void i82801ix_lpc_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - -/* To build emulation/qemu-q35 with CHROMEOS. */ -void *gnvs_chromeos_ptr(struct global_nvs *gnvs) -{ - return 0; -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 046cc2b5d5..0483447e94 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -7,7 +7,7 @@ #include <southbridge/intel/common/pmutil.h> #include "i82801ix.h" -#include "nvs.h" +#include <soc/nvs.h> #if !CONFIG(SMM_TSEG) /* For qemu/x86-q35 to build properly. */ diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 687cb45924..bd553eea76 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 9885bc0419..f4893c2ea4 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -23,4 +23,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801jx/include + endif diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h index 96c0a40e05..96c0a40e05 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 26ba5d21e2..90650693e1 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -12,14 +12,12 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <string.h> #include "chip.h" #include "i82801jx.h" -#include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/acpi_pirq_gen.h> @@ -476,11 +474,6 @@ static void i82801jx_lpc_read_resources(struct device *dev) } } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 6a6c5b4c7f..03a6442eb1 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -4,11 +4,10 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> +#include <soc/nvs.h> #include <southbridge/intel/common/pmutil.h> #include "i82801jx.h" -#include "nvs.h" - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index c54c7e4d6c..cea0efed97 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -8,6 +8,7 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select IOAPIC select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 277f686ba9..643687f0c8 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -36,4 +36,6 @@ romstage-y += ../bd82x6x/early_rcba.c romstage-y += early_cir.c romstage-y += early_usb.c +CPPFLAGS_common += -I$(src)/southbridge/intel/ibexpeak/include + endif diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h index bc18c2584d..bc18c2584d 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2a612ba517..9bc8e6be30 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -20,10 +20,10 @@ #include <cpu/x86/smm.h> #include "chip.h" #include "pch.h" -#include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/spi.h> +#include <soc/nvs.h> #define NMI_OFF 0 @@ -541,11 +541,6 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - void soc_fill_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e83a9de2fb..41f92b5fa0 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -8,13 +8,12 @@ #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/model_2065x/model_2065x.h> +#include <soc/nvs.h> #include <southbridge/intel/common/finalize.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/ibexpeak/me.h> #include "pch.h" -#include "nvs.h" - /* We are using PCIe accesses for now * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index a88a9a8bc2..7ad3c00027 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -8,6 +8,7 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 9694cc377f..d0b342b83a 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -46,4 +46,6 @@ endif verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c +CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include + endif diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index e699c5d8e2..aa6e6508cb 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -5,9 +5,9 @@ #include <acpi/acpigen.h> #include <string.h> #include <version.h> +#include <soc/nvs.h> #include "pch.h" -#include "nvs.h" static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) { diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h index 154e285a4a..154e285a4a 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a561f55776..4868441aaf 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -16,12 +16,12 @@ #include <string.h> #include "chip.h" #include "iobp.h" -#include "nvs.h" #include "pch.h" #include <acpi/acpigen.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/spi.h> +#include <soc/nvs.h> #define NMI_OFF 0 @@ -679,21 +679,6 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - -uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs) -{ - return &gnvs->cbmc; -} - -void *gnvs_chromeos_ptr(struct global_nvs *gnvs) -{ - return &gnvs->chromeos; -} - void soc_fill_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index d212d88621..0687cec6a1 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -7,10 +7,10 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <soc/nvs.h> #include "chip.h" #include "iobp.h" #include "pch.h" -#include "nvs.h" /* Enable clock in PCI mode */ static void serialio_enable_clock(struct resource *bar0) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index bd445008d3..22845ec518 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -14,10 +14,10 @@ #include <southbridge/intel/common/finalize.h> #include <northbridge/intel/haswell/haswell.h> #include <cpu/intel/haswell/haswell.h> +#include <soc/nvs.h> #include <smmstore.h> #include "me.h" #include "pch.h" -#include "nvs.h" int southbridge_io_trap_handler(int smif) { |