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-rw-r--r--src/southbridge/amd/cimx/sb800/cfg.c2
-rw-r--r--src/southbridge/amd/cimx/sb900/early.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 4487df3787..b52918d303 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -101,7 +101,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
#endif
/* LPC */
/* SuperIO hardware monitor register access */
- sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM;
+ sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM);
/*
* GPP. default configure only enable port0 with 4 lanes,
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index 1109290bc7..5ebe47e5fb 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -40,7 +40,7 @@ void sb_poweron_init(void)
outb(0xEA, 0xCD6);
data = inb(0xCD7);
data &= !BIT0;
- if (!CONFIG_PCIB_ENABLE) {
+ if (!CONFIG(PCIB_ENABLE)) {
data |= BIT0;
}
outb(data, 0xCD7);