diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-07 17:07:26 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-25 11:03:49 +0000 |
| commit | 5d1f9a009647c741e8587015b14f1e852e1c489e (patch) | |
| tree | b6e87bac2f8a578b7bee6b73111e04bd3750eeb8 /src/southbridge/amd | |
| parent | 2de19038beffa154eefe40755b607aa9f94d9f9f (diff) | |
Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)
This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/cfg.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/early.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 4487df3787..b52918d303 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -101,7 +101,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) #endif /* LPC */ /* SuperIO hardware monitor register access */ - sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM; + sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM); /* * GPP. default configure only enable port0 with 4 lanes, diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 1109290bc7..5ebe47e5fb 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -40,7 +40,7 @@ void sb_poweron_init(void) outb(0xEA, 0xCD6); data = inb(0xCD7); data &= !BIT0; - if (!CONFIG_PCIB_ENABLE) { + if (!CONFIG(PCIB_ENABLE)) { data |= BIT0; } outb(data, 0xCD7); |