diff options
Diffstat (limited to 'src/southbridge/amd/cimx/sb800')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/cfg.c | 5 |
3 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index b5f932534a..681c8814a2 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -27,5 +27,9 @@ if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" + +config SB_SUPERIO_HWM + bool + default n endif #SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 89b4dc3c85..164a65156f 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -120,6 +120,7 @@ typedef union _PCI_ADDR { #define cimIrConfigDefault 0x00 // Disable #define cimSpiFastReadEnableDefault 0x01 // Enable #define cimSpiFastReadSpeedDefault 0x01 // 33 MHz +#define cimSioHwmPortEnableDefault FALSE // GPP/AB Controller #define cimNbSbGen2Default TRUE #define cimAlinkPhyPllPowerDownDefault TRUE diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 57ff7181af..45a460be4f 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -50,6 +50,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS; sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS; sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; @@ -94,6 +95,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN; sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; + /* LPC */ + /* SuperIO hardware monitor register access */ + sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM; + /* * GPP. default configure only enable port0 with 4 lanes, * configure in devicetree.cb would overwrite the default configuration |